Method and circuit for communication between a module and a bus controller in a wafer-scale integrated circuit system

A bus system on a semiconductor device for communication between a communications module which is one of a plurality of communications modules and a bus master, said bus system comprising:

• a hierarchical bus connecting said bus master and said communications modules;
• a plurality of programmable bus transceivers connected to said hierarchical bus;
• means for selectively enabling said bus transceivers in response to a plurality of bus control signals transmitted on said hierarchical bus, and for selectively disabling said bus transceivers in response to said plurality of bus control signals, thereby dynamically controlling the configuration of said bus system;
• means for asynchronously transferring said bus control signals from said bus master to said communications module;
• and
• means for source-synchronously transferring command, data, address and clock signals between said communications module and said bus master.

A programmable bus transceiver for a hierarchical bus having a plurality of lines, comprising:

• a plurality of bi-directional, tri-state buffers for buffering signals in each bus line of said hierarchical bus along one of two opposite bus directions;
• an identification register for storing an address of said bus transceiver;
• a comparator for comparing a current address on said hierarchical bus with the address of said bus transceiver;
• and
• a control register for enabling output of said transceiver and controlling said directions along which said signals are buffered, wherein said bus transceiver is configured in response to control signals written to said control register, and wherein said control signals are written from said hierarchical bus to said control register when said current address matches the address of said bus transceiver.

A circuit comprising:

• a plurality of communicating modules;
• a source device;
• a bus having data paths and clock paths connecting said communicating modules and said source device;
• and
• clock frequency programming means located within each of said communicating modules for selecting a frequency of communication between at least one of said communicating modules and said source device, wherein each of said clock frequency programming means generates a clock signal having a frequency corresponding to said selected frequency of communication in response to a clock select signal transmitted from said source device to said communicating modules.