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AssigneeYokogawa Electric Corporation
InventorsHayato Waki, Shouji Igarashi
Estimating the term…
In a data processing apparatus 11, a buffer memory BM including a first buffer memory RM1, a second buffer memory MM1, a third buffer memory RM2, and a fourth buffer memory MM2, stores therein data that is formed of a plurality of bits, and a CPU 11A reads the data from the buffer memory BM, performs bit inversion on the plurality of bits to generate bit inverted data in which a value of each of the bits is inverted, writes the bit inverted data in the buffer memory BM at a first time, reads the data from the buffer memory BM at a second time that is later than the first time, compares first data that is bit inverted data that is written in the buffer memory BM at the first time and second data that is bit inverted data that is read from the buffer memory BM at the second time, and determines presence of a failure in the buffer memory BM.
A data processing apparatus comprising:
A memory failure determination method implemented by a processor, the memory failure determination method comprising:
A non-transitory computer readable recording medium having stored therein a memory failure determination program that causes a computer to execute a process, the process comprising:
Dependencies are inferred from the claim text.