Method for performing aging test on semiconductor used for neural network
AssigneeDeepx Co., Ltd.
InventorLok Won Kim
Life of this patent
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Abstract
Provided is a method for performing an aging test on a neural processing unit (NPU) with a capability of a runtime test. The method may comprise: performing an aging test on the NPU which comprises a plurality of functional components. The plurality of functional components may comprise at least one memory and plural processing elements. The performing of the aging test may include: performing a scan test on the NPU to verify whether at least one functional component in the NPU is defective or not; and performing a memory test on the at least one memory. At least one of the scan test and the memory test may be repeatedly performed to put a stress on the NPU for the aging test. The aging test may be repeated by a predetermined number.
Claims20
A method for performing an aging test on a neural processing unit (NPU) with a capability of a runtime test, comprising:
- performing an aging test on the NPU having a plurality of functional components,
- wherein the plurality of functional components comprise at least one memory and a plurality of processing elements,
- wherein the performing of the aging test includes:
- performing a scan test on the NPU to verify whether at least one functional component of the plurality of functional components in the NPU is defective or not;
- and
- performing a memory test on the at least one memory,
- wherein at least one of the scan test and the memory test is repeatedly performed to put a stress on the NPU for the aging test, and
- wherein the aging test is repeated by a predetermined number.
A method for performing an aging test on a system on chip (SoC) with a first capability for an artificial neural network and a second capability of a runtime test, the method comprising:
- performing an aging test on the SoC having a plurality of electronic circuitry having a plurality of functional components,
- wherein the plurality of functional components comprise at least one neural processing unit (NPU), at least one memory and a system bus,
- wherein the performing of the aging test includes:
- performing a scan test on the SoC to verify whether at least one functional component of the plurality of functional components in the SoC is defective or not;
- and
- performing a memory test on SoC,
- wherein at least one of the scan test and the memory test is repeatedly performed to put a stress on the SoC for the aging test, and
- wherein the aging test is repeated by a predetermined number.
Dependencies are inferred from the claim text.