Hybrid built-in system test switching circuitry for embedded memory testing

A system-on-chip integrated circuit, comprising:

• dynamic built-in system test (BIST) switching circuitry configured to generate one or more memory control signals based on a test state;
• and
• embedded memory configured to receive the one or more memory control signals from the dynamic BIST switching circuitry, the embedded memory further comprising:
• fixed BIST switching circuitry configured to generate one or more data transmission signals based on the test state,
• wherein the fixed BIST switching circuitry is internal to the embedded memory;
• wherein the dynamic BIST switching circuitry is external to the embedded memory.

A system-on-chip integrated circuit, comprising:

• dynamic built-in system test (BIST) switching circuitry configured to generate one or more data transmission signals based on a test state;
• and
• embedded memory configured to receive the one or more data transmission signals from the dynamic BIST switching circuitry, the embedded memory further comprising:
• fixed BIST switching circuitry configured to generate one or more memory control signals based on the test state,
• wherein the fixed BIST switching circuitry is internal to the embedded memory;
• wherein the dynamic BIST switching circuitry is external to the embedded memory.