G11C 16/3431
Circuits or methods to detect disturbed nonvolatile memory cells
Official title: {Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step}
G11C16/3431 (Circuits or methods to detect disturbed nonvolatile memory cells) appears on 886 US grants and 773 published applications in this corpus.
Search patents in G11C- Granted patents
- 886
- Published applications
- 773
- Assignees
- 204
- Inventors
- 1,295
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 3 | 0 |
| 1978 | 1 | 0 |
| 1979 | 1 | 0 |
| 1980 | 1 | 0 |
| 1981 | 1 | 0 |
| 1982 | 2 | 0 |
| 1983 | 5 | 0 |
| 1984 | 3 | 0 |
| 1985 | 6 | 0 |
| 1986 | 1 | 0 |
| 1987 | 3 | 0 |
| 1988 | 2 | 0 |
| 1989 | 3 | 0 |
| 1990 | 4 | 0 |
| 1991 | 0 | 0 |
| 1992 | 1 | 0 |
| 1993 | 2 | 0 |
| 1994 | 3 | 0 |
| 1995 | 8 | 0 |
| 1996 | 8 | 0 |
| 1997 | 13 | 0 |
| 1998 | 16 | 0 |
| 1999 | 18 | 0 |
| 2000 | 18 | 0 |
| 2001 | 10 | 3 |
| 2002 | 12 | 14 |
| 2003 | 14 | 24 |
| 2004 | 23 | 21 |
| 2005 | 20 | 20 |
| 2006 | 12 | 23 |
| 2007 | 27 | 34 |
| 2008 | 25 | 36 |
| 2009 | 31 | 32 |
| 2010 | 29 | 34 |
| 2011 | 33 | 23 |
| 2012 | 25 | 21 |
| 2013 | 24 | 25 |
| 2014 | 40 | 40 |
| 2015 | 34 | 38 |
| 2016 | 43 | 32 |
| 2017 | 45 | 40 |
| 2018 | 44 | 40 |
| 2019 | 40 | 42 |
| 2020 | 53 | 51 |
| 2021 | 39 | 34 |
| 2022 | 40 | 32 |
| 2023 | 30 | 37 |
| 2024 | 33 | 34 |
| 2025 | 24 | 24 |
| 2026 | 13 | 19 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Cascade model for determining read level voltage offsets based on wordline group memory cells29 Sep 2026US 12,749,541 B2Micron Technology, Inc.
- Performing block-level media management operations for block stripes in a memory device25 Aug 2026US 12,718,896 B2Micron Technology, Inc.
- Memory device performing leakage detection operation7 Jul 2026US 12,676,199 B2Samsung Electronics Co., Ltd.
- Memory management method, memory storage device and memory control circuit unit with capability to reduce bit error rate of data2 Jun 2026US 12,646,552 B2Phison Electronics Corp.
- Read disturb detection in a memory system26 May 2026US 12,640,211 B2Micron Technology, Inc.
- Accelerating program-erase cycles on memory devices24 Sep 2026US 2026/0288604 A1Micron Technology, Inc.
- Dual step multi-level cell program method for non-volatile memory24 Sep 2026US 2026/0290477 A1Silicon Storage Technology, Inc.
- Method for Reading Data Stored in a Flash Memory According to a Voltage Characteristic and Memory Controller Thereof27 Aug 2026US 2026/0253646 A1Silicon Motion, Inc.
- Non-periodic read disturb scan27 Aug 2026US 2026/0253652 A1Micron Technology, Inc.
- Background data refresh in storage devices20 Aug 2026US 2026/0245639 A1SK Hynix NAND Product Solutions Corp. (dba Solidigm)
Most cited
By later US patents
- Signature filter system544US 4,944,036 A1990
- Soft errors handling in EEPROM devices538US 5,657,332 ASanDisk Corporation · 1997
- Method and apparatus for storing data in a NAND flash memory506US 8,437,189 B1Marvell International Ltd. · 2013
- Soft errors handling in EEPROM devices433US 5,532,962 ASanDisk Corporation · 1996
- Flash memory with targeted read scrub algorithm346US 9,053,808 B2SanDisk Technologies LLC · 2015