Memory management method, memory storage device and memory control circuit unit with capability to reduce bit error rate of data

A memory storage device, comprising:

• a connection interface unit, configured to couple to a host system;
• a rewritable non-volatile memory module;
• and
• a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module,
• wherein the memory control circuit unit is configured to:
• detect a status of the rewritable non-volatile memory module;
• determine to perform a data refresh operation on the rewritable non-volatile memory module according to a first-type value relative relationship between a first evaluation value and a first threshold value and a second-type value relative relationship between a second evaluation value and a second threshold value;
• and
• determine not to perform any data refresh operation on the rewritable non-volatile memory module according to a third-type value relative relationship between the first evaluation value and the first threshold value and a fourth-type value relative relationship between the second evaluation value and the second threshold value,
• wherein the first evaluation value related to a first physical unit in the rewritable non-volatile memory module, the second evaluation value related to a plurality of second physical units in the rewritable non-volatile memory module, and the data refresh operation is configured to update data in the rewritable non-volatile memory module to reduce a bit error rate of the data.

A memory control circuit unit, configured to control a rewritable non-volatile memory module, the memory control circuit unit comprising:

• a host interface, configured to couple to a host system;
• a memory interface, configured to couple to the rewritable non-volatile memory module;
• and
• a memory management circuit, coupled to the host interface and the memory interface,
• wherein the memory control circuit unit is configured to:
• detect a status of the rewritable non-volatile memory module;
• and
• determine to perform a data refresh operation on the rewritable non-volatile memory module according to a first-type value relative relationship between a first evaluation value and a first threshold value and a second-type value relative relationship between a second evaluation value and a second threshold value;
• and
• determine not to perform any data refresh operation on the rewritable non-volatile memory module according to a third-type value relative relationship between the first evaluation value and the first threshold value and a fourth-type value relative relationship between the second evaluation value and the second threshold value,
• wherein the first evaluation value related to a first physical unit in the rewritable non-volatile memory module, the second evaluation value related to a plurality of second physical units in the rewritable non-volatile memory module, and the data refresh operation is configured to update data in the rewritable non-volatile memory module to reduce a bit error rate of the data.

A memory storage device, comprising:

• a connection interface unit, configured to couple to a host system;
• a rewritable non-volatile memory module;
• and
• a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module,
• wherein the memory control circuit unit is configured to obtain a performance evaluation value according to data transmission amount per unit time between the memory storage device and the host system and determine whether to perform a data refresh operation on the rewritable non-volatile memory module according to the performance evaluation value, and
• the data refresh operation is configured to update data in the rewritable non-volatile memory module to reduce a bit error rate of the data.