Dual step multi-level cell program method for non-volatile memory

A system, comprising:

• n banks of flash memory cells;
• and
• circuitry to:
• store (n−1) partitions of a first image of code in a first set of banks in single-level cell format, wherein the first set of banks comprise (n−1) of the n banks of flash memory cells;
• and
• store (n−1) partitions of the first image as first significant bits and (n−1) partitions of a second image of code as second significant bits in a second set of banks in dual step multi-level cell format, wherein the second set of banks comprise (n−1) of the n banks and the second set of banks comprises a bank not contained in the first set of banks, and wherein the first significant bits are either least significant bits or most significant bits of the flash memory cells, and the second significant bits are the other of the least significant bits and the most significant bits of the flash memory cells.

A system comprising:

• n banks of flash memory cells;
• and
• circuitry to:
• store (n−1) partitions of a first image of code as first significant bits in a first set of banks in dual step multi-level cell format, wherein the first set of banks comprise (n−1) of the n banks of flash memory cells;
• and
• store (n−1) partitions of a second image of code as second significant bits in the first set of banks in dual step multi-level cell format, wherein the first significant bits are either least significant bits or most significant bits of the flash memory cells, and the second significant bits are the other of the least significant bits and the most significant bits of the flash memory cells.