Read disturb detection in a memory system
AssigneeMicron Technology, Inc.
InventorsDeping He, Chun Sum Yeung
Life of this patent
Estimating the term…
Abstract
Methods, systems, and devices for read disturb detection in a memory system are described. A memory system may perform a read operation on a set of memory cells using a read voltage that is between a first target threshold voltage for the set of memory cells and a second target threshold voltage for the set of memory cells. The memory system may determine, based on a quantity of memory cells with a threshold voltage greater than the read voltage being greater than a threshold quantity, a bit error rate for the set of memory cells. And the memory system may determine whether to perform a refresh operation on the set of memory cells based on the bit error rate for the set of memory cells.
Claims21
A method, comprising:
- performing a read operation on a set of memory cells using a read voltage that is between a first target threshold voltage for the set of memory cells and a second target threshold voltage for the set of memory cells;
- transferring, based at least in part on a quantity of memory cells with a threshold voltage greater than the read voltage being greater than a threshold quantity, data read from the set of memory cells to a decoder to determine a bit error rate for the set of memory cells;
- performing, based at least in part on the bit error rate determined by the decoder being greater than or equal to a threshold bit error rate, a second read operation on the set of memory cells using a second read voltage that is lower than the read voltage;
- and
- determining whether to perform a refresh operation on the set of memory cells based at least in part on performing the second read operation on the set of memory cells.
A non-transitory computer-readable medium storing code comprising instructions which, when executed by one or more processors of a memory system, cause the memory system to:
- perform a read operation on a set of memory cells using a read voltage that is between a first target threshold voltage for the set of memory cells and a second target threshold voltage for the set of memory cells;
- transfer, based at least in part on a quantity of memory cells with a threshold voltage greater than the read voltage being greater than a threshold quantity, data read from the set of memory cells to a decoder to determine a bit error rate for the set of memory cells;
- perform, based at least in part on the bit error rate determined by the decoder being greater than or equal to a threshold bit error rate, a second read operation on the set of memory cells using a second read voltage that is lower than the read voltage;
- and
- determine whether to perform a refresh operation on the set of memory cells based at least in part on performing the second read operation on the set of memory cells.
A memory system, comprising:
- one or more memory devices;
- and
- one or more controllers coupled with the one or more memory devices and configured to cause the memory system to:
- perform a read operation on a set of memory cells using a read voltage that is between a first target threshold voltage for the set of memory cells and a second target threshold voltage for the set of memory cells;
- transfer, based at least in part on a quantity of memory cells with a threshold voltage greater than the read voltage being greater than a threshold quantity, data read from the set of memory cells to a decoder to determine a bit error rate for the set of memory cells;
- perform, based at least in part on the bit error rate determined by the decoder being greater than or equal to a threshold bit error rate, a second read operation on the set of memory cells using a second read voltage that is lower than the read voltage;
- and
- determine whether to perform a refresh operation on the set of memory cells based at least in part on performing the second read operation on the set of memory cells.
Dependencies are inferred from the claim text.