Memory device performing leakage detection operation

A memory device comprising:

• a memory cell array comprising a plurality of memory blocks, the plurality of memory blocks comprising a plurality of word lines, one or more string select lines, and one or more ground select lines;
• a pass transistor circuit comprising a plurality of pass transistors coupled to the plurality of memory blocks through the plurality of word lines, the one or more string select lines, and the one or more ground select lines;
• a row decoder configured to provide a block selection voltage to first terminals of the plurality of pass transistors and provide a driving voltage to second terminals of the plurality of pass transistors;
• a voltage generator configured to generate the block selection voltage and the driving voltage;
• and
• a control circuit configured to control the row decoder and the voltage generator and perform a leakage detection operation on the plurality of memory blocks,
• wherein the control circuit is further configured, when the leakage detection operation is performed on a target memory block from among the plurality of memory blocks, to:
• set, in a first operation of the leakage detection operation, the one or more string select lines and the one or more ground select lines to a cut-off voltage level by applying the driving voltage to a first plurality of second terminals of the plurality of pass transistors coupled to the one or more string select lines and the one or more ground select lines of the target memory block,
• wherein the control circuit is further configured to:
• set, in the first operation of the leakage detection operation, a plurality of first detection word lines from among the plurality of word lines of the target memory block to a first voltage level by applying the driving voltage to a second plurality of second terminals of the plurality of pass transistors coupled to the plurality of first detection word lines of the target memory block;
• set, in the first operation of the leakage detection operation, a plurality of second detection word lines from among the plurality of word lines of the target memory block to a second voltage level by applying the driving voltage to a third plurality of second terminals of the plurality of pass transistors coupled to the plurality of second detection word lines of the target memory block, the second voltage level being lower than the first voltage level;
• apply, in the first operation of the leakage detection operation, a first block selection voltage to a plurality of first terminals of the plurality of pass transistors coupled to the target memory block, the first block selection voltage having a third voltage level;
• apply, in a second operation of the leakage detection operation, a second block selection voltage to the plurality of first terminals of the plurality of pass transistors coupled to the target memory block, the second block selection voltage having the cut-off voltage level;
• and
• apply, in a third operation of the leakage detection operation, a third block selection voltage, to the plurality of first terminals of the plurality of pass transistors coupled to the target memory block, the third block selection voltage having a fourth voltage level, the fourth voltage level being lower than the third voltage level.

A memory device comprising:

• a memory cell array comprising a plurality of memory blocks, the plurality of memory blocks comprising a plurality of word lines, one or more string select lines, and one or more ground select lines;
• a pass transistor circuit comprising a plurality of pass transistors coupled to the plurality of memory blocks through the plurality of word lines, the one or more string select lines, and the one or more ground select lines;
• a row decoder configured to provide a block selection voltage to first terminals of the plurality of pass transistors and provide a driving voltage to second terminals of the plurality of pass transistors;
• a voltage generator configured to generate the block selection voltage and the driving voltage;
• and
• a control circuit configured to control the row decoder and the voltage generator and perform a leakage detection operation on the plurality of memory blocks,
• wherein the control circuit is further configured, when the leakage detection operation is performed on a target memory block from among the plurality of memory blocks, to:
• set a plurality of first detection word lines from among the plurality of word lines of the target memory block to a first voltage level by applying the driving voltage to a first plurality of second terminals of the plurality of pass transistors coupled to the plurality of first detection word lines of the target memory block;
• set a plurality of second detection word lines from among the plurality of word lines of the target memory block to a second voltage level by applying the driving voltage to a second plurality of second terminals of the plurality of pass transistors coupled to the plurality of second detection word lines of the target memory block, the second voltage level being lower than the first voltage level;
• and
• set the one or more string select lines and the one or more ground select lines to a third voltage level by applying the driving voltage to a third plurality of second terminals of the plurality of pass transistors coupled to the one or more string select lines and the one or more ground select lines of the target memory block, and
• wherein the control circuit is further configured to:
• set, in a first operation of the leakage detection operation, the plurality of word lines, the one or more string select lines, and the one or more ground select lines comprised by the target memory block by applying a first block selection voltage to a plurality of first terminals of the plurality of pass transistors coupled to the target memory block, the first block selection voltage having a fourth voltage level;
• apply, in a second operation of the leakage detection operation, a second block selection voltage to the plurality of first terminals of the plurality of pass transistors coupled to the target memory block, the second block selection voltage having a cut-off voltage level;
• and
• apply, in a third operation of the leakage detection operation, a third block selection voltage to the plurality of first terminals of the plurality of pass transistors coupled to the target memory block, the third block selection voltage having a fifth voltage level, the fifth voltage level being lower than the fourth voltage level.