G11C 11/5621
Using charge storage in a floating gate
Official title: {using charge storage in a floating gate}
G11C11/5621 (Using charge storage in a floating gate) appears on 9,504 US grants and 9,470 published applications in this corpus.
Search patents in G11C- Granted patents
- 9,504
- Published applications
- 9,470
- Assignees
- 550
- Inventors
- 6,135
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1979 | 1 | 0 |
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 2 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 2 | 0 |
| 1987 | 2 | 0 |
| 1988 | 0 | 0 |
| 1989 | 2 | 0 |
| 1990 | 1 | 0 |
| 1991 | 9 | 0 |
| 1992 | 13 | 0 |
| 1993 | 11 | 0 |
| 1994 | 11 | 0 |
| 1995 | 23 | 0 |
| 1996 | 38 | 0 |
| 1997 | 44 | 0 |
| 1998 | 120 | 0 |
| 1999 | 132 | 0 |
| 2000 | 141 | 0 |
| 2001 | 128 | 35 |
| 2002 | 114 | 101 |
| 2003 | 99 | 107 |
| 2004 | 92 | 122 |
| 2005 | 93 | 131 |
| 2006 | 105 | 148 |
| 2007 | 135 | 249 |
| 2008 | 224 | 384 |
| 2009 | 288 | 384 |
| 2010 | 291 | 380 |
| 2011 | 367 | 371 |
| 2012 | 401 | 372 |
| 2013 | 402 | 380 |
| 2014 | 475 | 441 |
| 2015 | 467 | 400 |
| 2016 | 501 | 434 |
| 2017 | 447 | 319 |
| 2018 | 365 | 335 |
| 2019 | 437 | 521 |
| 2020 | 562 | 607 |
| 2021 | 608 | 566 |
| 2022 | 516 | 607 |
| 2023 | 531 | 596 |
| 2024 | 569 | 605 |
| 2025 | 488 | 483 |
| 2026 | 246 | 392 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Enhanced read retry (ERR) for data recovery in flash memory6 Oct 2026US 12,755,797 B2SanDisk Technologies LLC
- Method of controlling a semiconductor memory including memory cells and a word line6 Oct 2026US 12,755,800 B2Kioxia Corporation
- Memory devices including tri-state memory cells22 Sep 2026US 12,744,082 B2Micron Technology, Inc.
- Nonvolatile memory15 Sep 2026US 12,738,316 B2Kioxia Corporation
- Memory system performing read operation using read voltage15 Sep 2026US 12,738,324 B2Kioxia Corporation
- Optimization of soft bit windows based on signal and noise characteristics of memory cells8 Oct 2026US 2026/0311755 A1Micron Technology, Inc.
- Bias voltage control for sub-block groups in a memory device8 Oct 2026US 2026/0311766 A1Micron Technology, Inc.
- Alternative erase schemes for reliability-risk word lines8 Oct 2026US 2026/0311777 A1Micron Technology, Inc.
- Selective use of a word line monitoring procedure for reliability-risk word lines8 Oct 2026US 2026/0311782 A1Micron Technology, Inc.
- Method for forming memory device8 Oct 2026US 2026/0313870 A1National Taiwan University
Most cited
By later US patents
- Multi-state EEprom read and write circuits and techniques1,175US 5,172,338 ASunDisk Corporation · 1992
- Multi-state memory1,008US 6,222,762 B1SanDisk Corporation · 2001
- Multi-state EEPROM having write-verify control circuit972US 5,570,315 AKabushiki Kaisha Toshiba · 1996
- Semiconductor device and memory system940US 6,046,935 AKabushiki Kaisha Toshiba · 2000
- High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates827US 5,867,429 ASanDisk Corporation · 1999