Memory devices including tri-state memory cells

A memory device comprising:

• a bank comprising:
• between eight and ten continuous arrays of tri-state memory cells, each of the tri-state memory cells accessible by a respective bit line, each of the continuous arrays comprising two column planes or three column planes, each of the column planes associated with sixty-four respective column-select lines, and groups of the bit lines associated with respective column-select lines, wherein each of the respective bit lines is comprised of a pair of bit lines and each of the column-select lines is associated with a respective group of from six bit lines to twelve bit lines, wherein one bit line of the pair of bit lines is coupled to a first sense amplifier and another bit line of the pair of bit lines coupled to a second, different sense amplifier;
• and
• a number of sub-word-line drivers interspersed between the number of continuous arrays.

A memory device comprising:

• between eight continuous arrays and ten continuous arrays comprising respective numbers of pairs of tri-state memory cells, each of the continuous arrays comprising:
• two column planes or three column planes, each column-plane associated with sixty-four respective column-select lines each associated with groups of pairs of bit lines, wherein each column plane is associated with between three hundred eighty-four pairs of bit lines and seven hundred sixty eight pairs of bit lines and wherein each of the column-select lines is associated with a respective group of between six pairs of bit lines and twelve pairs of bit lines;
• and
• each of the pairs of tri-state memory cells comprising:
• a first tri-state cell to store a first voltage level that is one of three voltage levels, the first tri-state cell accessible by a first pair of bit lines, the first pair of bit lines to carry a first two binary signals based on the first voltage level, each bit line of each first pair of bit lines coupled to different sense amplifiers;
• and
• a second tri-state cell to store a second voltage level that is one of the three voltage levels, the second tri-state cell accessible by a second pair of bit lines, the second pair of bit lines to carry a second two binary signals based on the second voltage level, each bit line of each second pair of bit lines coupled to different sense amplifiers;
• three input/output lines for each pair of tri-state memory cells, the three input/output lines to carry three binary signals based on the first voltage level and the second voltage level of the pair of tri-state memory cells;
• logic to translate respective first two binary signals and second two binary signals of a pair of tri-state memory cells into respective three binary signals and to translate the respective three binary signals into the respective first two binary signals and second two binary signals;
• and
• a number of sub-word-line drivers interspersed between the number of continuous arrays.