G11C 11/406
Management or control of the refreshing or charge-regeneration cycles
G11C11/406 (Management or control of the refreshing or charge-regeneration cycles) appears on 4,856 US grants and 4,483 published applications in this corpus.
Search patents in G11C- Granted patents
- 4,856
- Published applications
- 4,483
- Assignees
- 531
- Inventors
- 4,647
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 6 | 0 |
| 1977 | 8 | 0 |
| 1978 | 5 | 0 |
| 1979 | 7 | 0 |
| 1980 | 9 | 0 |
| 1981 | 9 | 0 |
| 1982 | 16 | 0 |
| 1983 | 10 | 0 |
| 1984 | 7 | 0 |
| 1985 | 10 | 0 |
| 1986 | 11 | 0 |
| 1987 | 21 | 0 |
| 1988 | 14 | 0 |
| 1989 | 19 | 0 |
| 1990 | 25 | 0 |
| 1991 | 20 | 0 |
| 1992 | 15 | 0 |
| 1993 | 24 | 0 |
| 1994 | 44 | 0 |
| 1995 | 38 | 0 |
| 1996 | 39 | 0 |
| 1997 | 48 | 0 |
| 1998 | 54 | 0 |
| 1999 | 65 | 0 |
| 2000 | 70 | 0 |
| 2001 | 86 | 45 |
| 2002 | 105 | 141 |
| 2003 | 141 | 169 |
| 2004 | 131 | 165 |
| 2005 | 158 | 217 |
| 2006 | 162 | 185 |
| 2007 | 179 | 191 |
| 2008 | 158 | 151 |
| 2009 | 137 | 138 |
| 2010 | 131 | 109 |
| 2011 | 119 | 113 |
| 2012 | 107 | 114 |
| 2013 | 122 | 120 |
| 2014 | 137 | 176 |
| 2015 | 179 | 188 |
| 2016 | 206 | 185 |
| 2017 | 216 | 180 |
| 2018 | 183 | 165 |
| 2019 | 194 | 207 |
| 2020 | 224 | 220 |
| 2021 | 199 | 222 |
| 2022 | 212 | 247 |
| 2023 | 220 | 251 |
| 2024 | 210 | 242 |
| 2025 | 224 | 194 |
| 2026 | 122 | 148 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
- G11C 11/40615Internal triggering or timing of refresh1,583
- G11C 11/40611External triggering or timing of internal or partially internal refresh operations967
- G11C 11/40618Refresh operations over multiple banks or interleaving926
- G11C 11/40622Partial refresh of memory arrays629
- G11C 11/40603Arbitration, priority and concurrent access to memory cells for read/write or refresh579
- G11C 11/40626Temperature related aspects of refresh operations568
- G11C 11/40607Refresh operations in memory devices with an internal cache or data buffer196
Recent patents
- Clock converting circuit with symmetric structure6 Oct 2026US 12,754,585 B2Samsung Electronics Co., Ltd.
- Mitigation of refresh management row hammer6 Oct 2026US 12,755,771 B2Rambus Inc.
- Performing serialized update procedures during a refresh period29 Sep 2026US 12,749,521 B2Micron Technology, Inc.
- Semiconductor memory device and method for controlling the same for row-hammer refresh operations without reducing the performance of normal refresh operations29 Sep 2026US 12,749,522 B2Winbond Electronics Corp.
- Apparatuses and methods for access based targeted refresh operations29 Sep 2026US 12,749,523 B2Micron Technology, Inc.
- Detection and mitigation of attacks on row hammer mitigation circuits8 Oct 2026US 2026/0311739 A1Micron Technology, Inc.
- Semiconductor device and memory device including sampling circuit1 Oct 2026US 2026/0301791 A1SK hynix Inc.
- Apparatuses and methods for controlling steal rates1 Oct 2026US 2026/0301792 A1Lodestar Licensing Group LLC
- Dynamic memory refresh interval to reduce bandwidth penalty1 Oct 2026US 2026/0301793 A1Micron Technology, Inc.
- Staggered bank refresh in 3d-dram24 Sep 2026US 2026/0290422 A1Micron Technology, Inc.
Most cited
By later US patents
- Data storage device and refreshing method for use with such device605US 7,170,807 B2Innovative Silicon S.A. · 2007
- Digit line comparison circuits429US 8,279,683 B2Micron Technology, Inc. · 2012
- High speed DRAM architecture with uniform access latency419US 8,503,250 B2Mosaid Technologies Incorporated · 2013
- Semiconductor memory device and method of operating same339US 7,085,156 B2Innovative Silicon S.A. · 2006
- Merging write cycles by comparing at least a portion of the respective write cycle addresses296US 6,356,485 B1Integrated Device Technology, Inc. · 2002