G11C 11/40603
Arbitration, priority and concurrent access to memory cells for read/write or refresh
Official title: {Arbitration, priority and concurrent access to memory cells for read/write or refresh operations}
G11C11/40603 (Arbitration, priority and concurrent access to memory cells for read/write or refresh) appears on 579 US grants and 656 published applications in this corpus.
Search patents in G11C- Granted patents
- 579
- Published applications
- 656
- Assignees
- 124
- Inventors
- 808
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 1 | 0 |
| 1987 | 0 | 0 |
| 1988 | 1 | 0 |
| 1989 | 1 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 1 | 0 |
| 1997 | 1 | 0 |
| 1998 | 2 | 0 |
| 1999 | 0 | 0 |
| 2000 | 0 | 0 |
| 2001 | 0 | 2 |
| 2002 | 3 | 5 |
| 2003 | 8 | 9 |
| 2004 | 11 | 29 |
| 2005 | 20 | 27 |
| 2006 | 36 | 26 |
| 2007 | 21 | 22 |
| 2008 | 12 | 10 |
| 2009 | 12 | 9 |
| 2010 | 12 | 6 |
| 2011 | 9 | 10 |
| 2012 | 5 | 3 |
| 2013 | 4 | 12 |
| 2014 | 9 | 17 |
| 2015 | 17 | 15 |
| 2016 | 23 | 13 |
| 2017 | 25 | 27 |
| 2018 | 26 | 21 |
| 2019 | 26 | 32 |
| 2020 | 34 | 35 |
| 2021 | 37 | 38 |
| 2022 | 43 | 68 |
| 2023 | 46 | 55 |
| 2024 | 49 | 55 |
| 2025 | 63 | 61 |
| 2026 | 19 | 49 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Performing serialized update procedures during a refresh period29 Sep 2026US 12,749,521 B2Micron Technology, Inc.
- Adjusting refresh rate during self-refresh state15 Sep 2026US 12,738,309 B2Micron Technology, Inc.
- Memory device and memory system for performing target refresh operation8 Sep 2026US 12,731,628 B2SK hynix Inc.
- Memory apparatus, refresh control circuit and row hammer refresh method1 Sep 2026US 12,725,648 B2Winbond Electronics Corp.
- Memory controller for memory with medium granularity refresh commands25 Aug 2026US 12,717,486 B2Advanced Micro Devices, Inc.
- Memory device having hidden refresh13 Aug 2026US 2026/0236165 A1Rambus Inc.
- Refresh Latency Indication for Refresh Operations13 Aug 2026US 2026/0237417 A1Micron Technology, Inc.
- Processing-in-memory (pim) operation aware refresh scheduling13 Aug 2026US 2026/0237418 A1QUALCOMM Incorporated
- Memory system, method of operating thereof, and controller13 Aug 2026US 2026/0237419 A1Yangtze Memory Technologies Co., Ltd.
- Self-Refresh Status Indication for Self-Refresh Exit6 Aug 2026US 2026/0229270 A1Micron Technology, Inc.
Most cited
By later US patents
- Dynamic memory supporting simultaneous refresh and data-access transactions204US 7,043,599 B1Rambus Inc. · 2006
- Semiconductor device with non-volatile memory and random access memory125US 6,791,877 B2Renesas Technology Corp. · 2004
- Semiconductor memory and method for operating the same93US 7,203,115 B2Fujitsu Limited · 2007
- Method, apparatus and system for responding to a row hammer event91US 9,286,964 B2Intel Corporation · 2016
- Memory device including refresh controller90US 9,691,466 B1SK hynix Inc. · 2017