Memory device and memory system for performing target refresh operation

A memory device, comprising:

• an active control circuit configured to generate an internal active signal and an internal precharge signal which are sequentially activated, in response to a precharge command, and generate a row active signal having a first activation section that is defined by an active command and the precharge command, and a second activation section that is defined by the internal active signal and the internal precharge signal, wherein the internal active signal is activated after a second delay time from an input of the precharge command, and the internal precharge signal is activated after a first delay time from an activation of the internal active signal;
• an address control circuit configured to generate a row address by selecting one of an active address and an adjacent address adjacent to the active address during the first activation section, and by selecting the remaining one during the second activation section;
• and
• a row control circuit configured, in response to the row active signal, a) to activate a word line corresponding to the row address during one of the first and second activation sections, and b) to refresh a word line corresponding to the adjacent address during the remaining one of the first and second activation sections.

An operating method of a memory device, the operating method comprising:

• generating an internal precharge signal after a first delay time from an input of an active command;
• activating at least one first word line corresponding to one of an active address and an adjacent address according to the active command, and deactivating the activated first word line according to the internal precharge signal;
• generating an internal active signal after a second delay time from an activation of the internal precharge signal;
• and
• activating at least one second word line corresponding to the remaining one of the active address and the adjacent address according to the internal active signal, and deactivating the activated second word line according to a precharge command.

An operating method of a memory device, the operating method comprising:

• activating at least one first word line corresponding to one of an active address and an adjacent address according to an active command, and deactivating the activated first word line according to a precharge command;
• generating an internal active signal after a second delay time from an input of the precharge command;
• generating an internal precharge signal after a first delay time from an activation of the internal active signal;
• and
• activating at least one second word line corresponding to the remaining one of the active address and the adjacent address according to the internal active signal, and deactivating the activated second word line according to the internal precharge signal.

A memory system comprising:

• a controller configured to provide an active command, a precharge command, and a row address;
• and
• a memory device configured to:
• generate an internal precharge signal and an internal active signal which are sequentially activated, in response to the active command, wherein the internal precharge signal is activated after a first delay time from an input of the active command, and the internal active signal is activated after a second delay time from an activation of the internal precharge signal,
• generate a row active signal having a first activation section that is defined by the active command and the internal precharge signal, and a second activation section that is defined by the internal active signal and the precharge command,
• activate a target word line corresponding to the row address during one of the first and second activation sections, and
• refresh an adjacent word line adjacent to the target word line during the remaining one of the first and second activation sections, in response to the row active signal.

A memory system comprising:

• a controller configured to provide an active command, a precharge command, and a row address;
• and
• a memory device configured to:
• generate an internal active signal and an internal precharge signal which are sequentially activated, in response to the precharge command, generate a row active signal having a first activation section that is defined by the active command and the precharge command, and a second activation section that is defined by the internal active signal and the internal precharge signal, wherein the internal active signal is activated after a second delay time from an input of the precharge command, and the internal precharge signal is activated after a first delay time from an activation of the internal active signal,
• activate a target word line corresponding to the row address during one of the first and second activation sections, and
• refresh an adjacent word line adjacent to the target word line during the remaining one of the first and second activation sections, in response to the row active signal.