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US 7,043,599 B1Granted
Dynamic memory supporting simultaneous refresh and data-access transactions
AssigneeRambus Inc.
InventorsFrederick A. Ware, Richard E. Perego
Life of this patent
Estimating the term…
Abstract
Described are dynamic memory systems that perform overlapping refresh and data-access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed to different banks. Two sets of address registers enable the system to simultaneously specify different banks for refresh and data-access transactions.
Claims95
A dynamic memory comprising:
- a. a first memory bank;
- b. a second memory bank;
- c. a request interface receiving first and second activate commands;
- d. a refresh register activating the first memory bank in response to the first activate command;
- and
- e. a data-access register activating the second memory bank in response to the second activate command;
- f. wherein the request interface activates the first and second memory banks substantially simultaneously.
4 more elements
A dynamic memory comprising:
- a. a first memory bank;
- b. a second memory bank;
- c. a refresh register activating the first memory bank;
- and
- d. a data-access register activating the second memory bank;
- e. wherein at least one of the refresh register and the data-access register includes a configurable delay register.
3 more elements
A dynamic memory comprising:
- a. a first memory bank;
- b. a second memory bank;
- c. a refresh register activating the first memory bank;
- and
- d. a data-access register activating the second memory bank;
- e. a request interface receiving a data-access command and a refresh command;
- and
- f. a request decoder having:
- i. a decoder input port connected to the request interface;
- ii. a first decoder output port connected to the refresh register;
- and
- iii. a second decoder output port connected to the data-access register;
- iv. wherein the request decoder decodes the data-access command and the refresh command.
10 more elements
A dynamic memory comprising:
- a. a first memory bank;
- b. a second memory bank;
- c. a refresh register activating the first memory bank;
- d. a data-access register activating the second memory bank;
- and
- e. a third memory bank, wherein the data access register activates the first memory bank at a first instant, the data-access register activates the second memory bank at a second instant, and the refresh register activates the third memory bank at a third instant, and wherein the first instant is spaced from the second instant by a minimum timing difference.
3 more elements
A dynamic memory comprising:
- a. a first memory bank;
- b. a second memory bank;
- c. a request interface coupled to the first and second memory banks, the request interface receiving a data-access command and a refresh command;
- d. a refresh register storing a first bank address identifying the first memory bank in response to the refresh command, wherein the refresh command initiates a first precharge operation;
- and
- e. a data-access register storing a second bank address identifying the second memory bank in response to the data-access command, wherein the data-access command initiates a second precharge operation substantially simultaneous with the first precharge operation.
3 more elements
A dynamic memory comprising:
- a. a first memory bank;
- b. a second memory bank;
- c. a refresh register storing a first bank address identifying the first memory bank for a refresh precharge command, wherein the refresh precharge command initiates a first precharge operation;
- and
- d. a data-access register storing a second bank address identifying the second memory bank for a data-access precharge command, wherein the data-access precharge command initiates a second precharge operation overlapping the first precharge operation;
- e. wherein at least one of the refresh register and the data-access register includes a configurable delay register.
3 more elements
A memory controller comprising:
- a. a transaction queue that provides a plurality of data access transactions on a data-access-transaction interconnect, wherein the transaction queue stores at least on historical memory transaction and at least one future memory transaction, the number of historical memory transactions is at least a second number of historical memory transactions that occurred over a preceding period t sub RC minus T sub RR wherein t sub RC is a row cycle time and T sub RR is a minimum time between two successive activate commands to different banks of the memory;
- b. a refresh transaction generator that provides a series of refresh transactions on a refresh-transaction interconnect;
- and
- c. a request generating circuit connected to the data-transaction interconnect and the refresh-transaction interconnect, wherein the request generating circuit decomposes the data-access-transactions into one or more data-access requests and decomposes the refresh transactions into one or more refresh requests.
1 more element
A dynamic memory comprising:
- a. a first memory bank;
- b. a second memory bank;
- c. a refresh activate register connected to the first and second memory banks;
- d. a refresh precharge register connected to the first and second memory banks;
- e. a data-access activate register connected to the first and second memory banks;
- and
- f. a data-access precharge register connected to the first and second memory banks.
4 more elements
A dynamic memory comprising:
- a. a refresh register;
- b. a data-access register;
- c. a first multiplexer having:
- i. a first multiplexer input terminal connected to the refresh register;
- ii. a second multiplexer input terminal connected to the data-access register;
- and
- iii. a first multiplexer output terminal;
- d. a second multiplexer having:
- i. a third multiplexer input terminal connected to the refresh register;
- ii. a fourth multiplexer input terminal connected to the data-access register;
- and
- iii. a second multiplexer output terminal;
- e. a first memory bank connected to the first multiplexer output terminal;
- and
- f. a second memory bank connected to the second multiplexer output terminal.
12 more elements
A dynamic memory comprising:
- a. a first memory bank;
- b. a second memory bank;
- c. a request interface receiving, at a first instant, a combined command specifying a data-access operation directed to the first memory bank and a refresh operation directed to the second bank;
- d. a refresh register within the request interface and activating, in response to the combined command, the first memory bank at a second instant;
- and
- e. a data-access register within the request interface and activating, in response to the combined command, the second memory bank at a third instant.
3 more elements
A dynamic memory comprising:
- a. a first memory bank;
- b. a second memory bank;
- c. a request interface receiving, at a first instant, a combined command specifying a data-access operation directed to the first memory bank and a refresh operation directed to the second bank;
- d. a refresh register within the request interface and activating, in response to the combined command, the first memory bank at a second instant;
- and
- e. a data-access register within the request interface and activating, in response to the combined command, the second memory bank at a third instant;
- f. wherein at least one of the refresh register and the data-access register includes a configurable delay register.
4 more elements
A dynamic memory comprising:
- a. a first memory bank;
- b. a second memory bank;
- c. a request interface receiving, at a first instant, a combined command specifying a precharge operation directed to the first memory bank and a precharge operation directed to the second memory bank;
- d. a refresh register within the request interface and activating, in response to the combined command, the first memory bank at a second instant;
- and
- e. a data-access register within the request interface and activating, in response to the combined command, the second memory bank at a third instant separated from the second instant.
3 more elements
A dynamic memory comprising:
- a. a first memory bank;
- b. a second memory bank;
- c. a request interface receiving, at a first instant, a combined command specifying a precharge operation directed to the first memory bank and a precharge operation directed to the second memory bank;
- d. a refresh register within the request interface and activating, in response to the combined command, the first memory bank at a second instant;
- and
- e. a data-access register within the request interface and activating, in response to the combined command, the second memory bank at a third instant separated from the second instant;
- f. wherein at least one of the refresh register and the data-access register includes a configurable delay register.
4 more elements
Dependencies are inferred from the claim text.