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US 7,203,115 B2Granted
Semiconductor memory and method for operating the same
AssigneeFujitsu Limited
InventorSatoshi Eto
Life of this patent
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AssigneeFujitsu Limited
InventorSatoshi Eto
Estimating the term…
A data additional circuit adds plural types of expectation data to be read from a refresh block to data read from other blocks, respectively, to generate plural read data strings. An error correction circuit detects errors for each read data string, and sets the most reliable result of the error detection results to be true. The error correction circuit decodes data to be read from the refresh block based on a true error detection result. Moreover, the error correction circuit corrects the error of the read data string corresponding to the true error detection result. Consequently, without extending the read cycle time, a refresh operation can be hid, and errors can be corrected simultaneously. By correcting a data error read from a bad memory cell of data retention characteristics, a refresh request interval can be extended, and power consumption during a standby period can be reduced.
A semiconductor memory comprising:
A method of operating a semiconductor memory having a plurality of data blocks with memory cells which store information data, a plurality of code blocks with memory cells that store code data to decode data stored in said data blocks, and a refresh control circuit which outputs refresh request signals to sequentially perform refresh operations on said data blocks and said code blocks, the method comprising the steps of:
Dependencies are inferred from the claim text.