Processing-in-memory (pim) operation aware refresh scheduling

An apparatus, comprising:

• one or more memories storing processor-executable code;
• and
• one or more processors coupled with the one or more memories and individually or collectively operable to execute the code to cause the apparatus to:
• initiate, by a memory controller of a memory device, execution of a PIM operation on a first plurality of memory banks of the memory device;
• select, by the memory controller of the memory device, a second plurality of memory banks of the memory device different than the first plurality of memory banks to execute a refresh operation based at least in part on knowledge of the initiating the execution of the PIM operation on the first plurality of memory banks;
• initiate, by the memory controller of the memory device, execution of the refresh operation on the second plurality of memory banks;
• and
• switch, in response to completing execution of the PIM operation on the first plurality of memory banks and by the memory controller of the memory device, execution of the refresh operation on the second plurality of memory banks to the first plurality of memory banks and execution of the PIM operation on the first plurality of memory banks to the second plurality of memory banks.

A non-transitory computer-readable medium storing code for wireless communications, the code comprising instructions executable by one or more processors to:

• initiate, by a memory controller of a memory device, execution of a PIM operation on a first plurality of memory banks of the memory device;
• select, by the memory controller of the memory device, a second plurality of memory banks of the memory device different than the first plurality of memory banks to execute a refresh operation based at least in part on knowledge of the initiating the execution of the PIM operation on the first plurality of memory banks;
• initiate, by the memory controller of the memory device, execution of the refresh operation on the second plurality of memory banks;
• and
• switch, in response to completing execution of the PIM operation on the first plurality of memory banks and by the memory controller of the memory device, execution of the refresh operation on the second plurality of memory banks to the first plurality of memory banks and execution of the PIM operation on the first plurality of memory banks to the second plurality of memory banks.