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US 9,691,466 B1Granted
Memory device including refresh controller
AssigneeSK hynix Inc.
InventorChang-Hyun Kim
Life of this patent
Estimating the term…
Abstract
A memory device may include: a target address generator suitable for storing one or more addresses for each time a refresh command is skipped, and for generating one or more target addresses for each of the stored addresses during a burst refresh operation; and a refresh controller suitable for refreshing a word line selected among a plurality of word lines of a memory bank based on the generated one or more target addresses during a target refresh operation.
Claims20
A memory device comprising:
- a target address generator configured to store one or more addresses for each time a refresh command is skipped, and generate one or more target addresses for each of the stored addresses during a burst refresh operation, wherein the target addresses are generated by adding or subtracting a set value to or from the stored addresses;
- and
- a refresh controller configured to refresh a word line selected among a plurality of word lines of a memory bank based on the generated one or more target addresses during a target refresh operation.
A memory device comprising:
- a plurality of word lines;
- a control signal generator configured to enable a control signal in response to a refresh command, enable the control signal at a set interval during a refresh skip operation, and disable the control signal during a burst refresh operation;
- a target address generator comprising a plurality of address storage units, and configured to sequentially primarily select the plurality of address storage units one by one whenever the control signal is activated and storing a row hammering address in the primarily selected address storage units, and sequentially secondarily select the plurality of address storage units one by one whenever the refresh operation is ended and generating a target address using addresses stored in the secondarily selected address storage units;
- and
- a refresh controller configured to refresh a word line corresponding to the target address among the plurality of word lines, during a target refresh operation.
2 more elements
A memory device comprising:
- a plurality of word lines coupled to a plurality of memory cells;
- a target address generator including at least two address storage units configured to store at least two row hammering addresses, and configured to generate a plurality of target addresses in response to the row hammering addresses during a burst refresh operation;
- and
- a refresh controller configured to refresh the memory cells coupled to a plurality of selected word lines among the word lines in response to the target addresses during the burst refresh operation,
- wherein the at least two row hammering addresses corresponds to a number of times where a refresh command is skipped.
2 more elements
Dependencies are inferred from the claim text.