Staggered bank refresh in 3d-dram
AssigneeMicron Technology, Inc.
InventorsHiromasa Takeda, Hiroki Fujisawa, Kyoichi Nagata
Life of this patent
Estimating the term…
Abstract
A 3D memory device includes memory banks. During refresh operations, responsive to a refresh signal and refresh address directed to a given bank, one or more word lines in a first portion of the bank are refreshed at a first time and one or more word lines in a second portion of the bank are refreshed at a second time after the first time. For example, one or more row control circuits associated with the bank provide a first sense amplifier enable signal to the first portion and a second sense amplifier enable signal to the second portion. The second sense amplifier enable signal is provided through a delay circuit to stagger the two signals in time.
Claims20
An apparatus comprising:
- a memory bank comprising a first portion and a second portion;
- at least one row control circuit configured to provide a first sense amplifier enable signal to the first portion and a second sense amplifier enable signal to the second portion responsive to a refresh signal;
- a delay circuit configured to delay the second sense amplifier enable signal relative to the first sense amplifier enable signal,
- wherein a first word line in the first portion is refreshed at a first time responsive to the first sense amplifier enable signal and a second word line in the second portion is refreshed at a second time responsive to the second sense amplifier enable signal.
A method comprising:
- receiving a refresh signal for a memory bank;
- providing a first sense amplifier enable signal to a first portion of the bank at a first time;
- and
- providing a second sense amplifier enable signal to a second portion of the bank at a second time.
An apparatus comprising:
- a first memory die comprising a memory bank comprising a plurality of memory cells in a 3D array;
- a second memory die comprising:
- a memory bank region positioned above the memory bank;
- a peripheral region;
- at least one row control circuit configured to receive a refresh signal associated with the bank and configured to refresh a first word line in the memory bank at a first time and a second word line at a second time, wherein the first and the second word line are associated with a same refresh address.
Dependencies are inferred from the claim text.