Semiconductor device and memory device including sampling circuit

Abstract

A semiconductor device includes: a sampling control circuit configured to select a coarse section from a plurality of coarse sections according to a first pattern signal during a sampling period, select a fine section from a plurality of fine sections according to a second pattern signal during the selected coarse section, and generate first to third sampling control signals having activated sections defined by the selected coarse section and the selected fine section; and a sampling circuit configured to sample an input address according to the first to third sampling control signals, respectively, to generate first to third sampling addresses, and schedule the first to third sampling addresses according to a sampling signal defining the sampling period to output an output address.

Dependencies are inferred from the claim text.