Data storage device and refreshing method for use with such device
AssigneeInnovative Silicon S.A.
InventorsPierre Fazan, Serguei Okhonin
Life of this patent
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Abstract
A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit 16, writing circuits 18 and a refreshing circuit 22 apply input signals to the data storage cells to reverse the variation of the physical parameter with time of at least those cells representing one of the binary logic states by causing a different variation in the physical parameter of cells in one of said states than in the other.
Claims24
A semiconductor memory array comprising:
- a plurality of memory cells, including a first memory cell and a second memory cell, wherein each memory cell of the plurality of memory cells includes an associated transistor having a source region, a drain region, an electrically floating body region disposed therebetween, and a gate disposed over the electrically floating body region, and wherein each memory cell further includes a charge in the body region of the associated transistor which varies with time and
- a first data state representative of a first charge provided in the body region of the associated transistor, and
- a second data state representative of a second charge in the body region of the associated transistor, wherein the first charge is greater than the second charge;
- and
- circuitry, coupled to the plurality of memory cells, to simultaneously apply first electrical signals to the first memory cell, which is in the first data state, and the second memory cell, which is in the second data state, wherein, in response to the first electrical signals, the first memory cell is refreshed and the second memory cell maintains the second data state.
A semiconductor memory array comprising:
- a plurality of memory cells, each memory cell including an associated transistor having a source region, a drain region, an electrically floating body region disposed therebetween, and a gate disposed over the electrically floating body region and separated therefrom by a dielectric, wherein each memory cell (i) further includes a charge in the body region of the associated transistor which varies with time and (ii) is reversibly programmed in:
- a first data state which is representative of a first charge state provided in the body region of the associated transistor;
- and
- a second data state which is representative of a second charge in the body region of the associated transistor, wherein the first charge is greater than the second charge;
- and
- circuitry, coupled to the plurality of memory cells, to apply first electrical signals to the plurality of memory cells wherein:
- memory cells that are in the first data state, in response to the first electrical signals, are refreshed, and
- memory cells that are in the second data state, in response to the first electrical signals, maintain the second data state.
A semiconductor memory array comprising:
- a plurality of memory cells arranged in a matrix form, each memory cell including an associated transistor having a source region, a drain region, an electrically floating body region disposed therebetween, and a gate disposed over the electrically floating body region and separated therefrom by a dielectric, wherein each memory cell is in:
- a first data state which is representative of a first charge in the body region of the associated transistor;
- or
- a second data state which is representative of a second charge in the body region of the associated transistor;
- and
- circuitry, coupled to the plurality of memory cells, to simultaneously apply first electrical signals to a plurality of memory cells wherein, in response to the first electrical signals, the memory cells:
- (1) that are in the first data state are refreshed, and (2) that are in the second data state maintain the second data state.
Dependencies are inferred from the claim text.