Digit line comparison circuits
AssigneeMicron Technology, Inc.
InventorDean A. Klein
Life of this patent
Estimating the term…
Abstract
A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.
Claims12
A digit line comparison circuit, comprising:
- a plurality of sense amplifiers, each of the sense amplifiers being connected between respective pairs of complementary digit lines;
- and
- a plurality of logic circuits coupled to the pairs of complementary digit lines respectively, each of the plurality of logic circuits being configured to provide a comparison indication based, at least in part, on leakage of the respective pairs of complementary digit lines.
A digit line comparison circuit, comprising:
- a plurality of sense amplifiers for use in a memory device having a plurality of complementary digit line pairs, each of the sense amplifiers comprising:
- a pair of cross-coupled PMOS transistors having their drains coupled to respective digit lines and their sources coupled to a first supply voltage;
- and
- a pair of cross-coupled NMOS transistors having their drains coupled to respective digit lines and their sources coupled to a second supply voltage;
- and
- a plurality of comparator circuits coupled to respective pairs of complementary digit lines, the plurality of comparator circuits being coupled to each other to provide a comparison indication indicative of a leakage of the voltages between the respective complementary digit line pairs.
A digit line comparison circuit, comprising:
- a plurality of sense amplifiers for use in a memory device having a plurality of complementary digit line pairs, each of the sense amplifiers comprising:
- a pair of cross-coupled PMOS transistors having their drains coupled to respective digit lines in each pair of complementary digit lines and their sources coupled to a first supply voltage;
- and
- a pair of cross-coupled NMOS transistors having their drains coupled to respective digit lines in each pair of complementary digit lines and their sources coupled to a second supply voltage;
- and
- a plurality of logic circuits coupled to the plurality of complementary digit line pairs respectively, each of the plurality of logic circuits configured to provide a comparison indication based, at least in part, on leakage of the respective plurality of complementary digit line pairs,
- wherein each of the plurality of logic circuits comprises a pair of cross-coupled transistors.
Dependencies are inferred from the claim text.