Clock converting circuit with symmetric structure

A clock converting circuit comprising:

• a first clock circuit configured to generate a first output clock signal based on a first input clock signal and a second input clock signal;
• a second clock circuit configured to generate a second output clock signal based on the second input clock signal and a third input clock signal;
• a third clock circuit configured to generate a third output clock signal based on the third input clock signal and a fourth input clock signal;
• and
• a fourth clock circuit configured to generate a fourth output clock signal based on the first input clock signal and the fourth input clock signal, wherein the first clock circuit includes:
• a first switch connected between a first input node and a first node, and configured to receive the first input clock signal at the first input node and operate in response to a first logic state of the second input clock signal;
• and
• a second switch connected between a power node and the first node, and configured to operate in response to a second logic state of the second input clock signal.

A clock converting circuit comprising:

• a first switch connected between a first input node and a first node, and configured to receive a first input clock signal at the first input node and operate in response to a first logic state of a second input clock signal;
• a second switch connected between a ground node and the first node, and configured to operate in response to a second logic state of the second input clock signal;
• and
• a third switch connected between a second input node and a second node, and configured to receive the second input clock signal at the second input node and operate in response to a second logic state of the first input clock signal,
• wherein a rising edge of a voltage waveform at the first node is determined in response to a rising edge of the first input clock signal, and a falling edge of the voltage waveform at the first node is determined in response to a rising edge of the second input clock signal.