G11C 11/06035
Bit core selection for writing or reading, by at least two coincident
Official title: {Bit core selection for writing or reading, by at least two coincident partial currents, e.g. "bit"- organised, 2L/2D, or 3D}
G11C11/06035 (Bit core selection for writing or reading, by at least two coincident) appears on 16 US grants and 9 published applications in this corpus.
Search patents in G11C- Granted patents
- 16
- Published applications
- 9
- Assignees
- 11
- Inventors
- 23
- Latest grant
- 1 Aug 2017
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 2 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 1 | 0 |
| 1991 | 0 | 0 |
| 1992 | 1 | 0 |
| 1993 | 0 | 0 |
| 1994 | 1 | 0 |
| 1995 | 1 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 0 | 0 |
| 1999 | 0 | 0 |
| 2000 | 0 | 0 |
| 2001 | 1 | 0 |
| 2002 | 0 | 0 |
| 2003 | 0 | 0 |
| 2004 | 0 | 0 |
| 2005 | 0 | 0 |
| 2006 | 0 | 0 |
| 2007 | 0 | 0 |
| 2008 | 0 | 0 |
| 2009 | 0 | 0 |
| 2010 | 0 | 1 |
| 2011 | 0 | 0 |
| 2012 | 0 | 1 |
| 2013 | 1 | 1 |
| 2014 | 2 | 1 |
| 2015 | 2 | 2 |
| 2016 | 2 | 1 |
| 2017 | 1 | 1 |
| 2018 | 0 | 0 |
| 2019 | 0 | 0 |
| 2020 | 0 | 0 |
| 2021 | 0 | 0 |
| 2022 | 0 | 0 |
| 2023 | 0 | 0 |
| 2024 | 0 | 0 |
| 2025 | 0 | 0 |
| 2026 | 0 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture1 Aug 2017US 9,721,653 B2SanDisk Technologies LLC
- Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines11 Oct 2016US 9,466,790 B2SanDisk Technologies LLC
- Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods2 Feb 2016US 9,251,860 B2Micron Technology, Inc.
- Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture17 Nov 2015US 9,190,134 B2SanDisk 3D LLC
- Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods30 Jun 2015US 9,070,442 B2Micron Technology, Inc.
- Integrated circuit memory devices having resistive memory cells therein and methods of operating same8 Jan 2026US 2026/0011366 A1Samsung Electronics Co., Ltd.
- Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines and a Single-Sided Word Line Architecture5 Jan 2017US 2017/0004881 A1SanDisk Technologies LLC
- Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines10 Mar 2016US 2016/0072058 A1SanDisk 3D LLC
- Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods1 Oct 2015US 2015/0279432 A1Micron Technology, Inc.
- Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods5 Mar 2015US 2015/0063024 A1Micron Technology, Inc.
Most cited
By later US patents
- Method of forming a ferromagnetic memory device64US 5,389,566 AMotorola, Inc. · 1995
- Ferromagnetic memory device51US 5,329,486 AMotorola, Inc. · 1994
- Core memory with improved sense-inhibit recovery time32US 3,982,233 AAmpex Corporation · 1976
- Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture19US 8,351,236 B2SanDisk 3D LLC · 2013
- Thin film magnetic core memory and method of making same18US 5,126,971 AMagnex Corporation · 1992