Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods

A memory device, comprising:

• a plurality of stacked memory cells respectively at different vertical levels;
• a select transistor above the plurality of stacked memory cells and configured to selectively couple the plurality of memory cells to a data line;
• and
• a plurality of pass transistors at substantially the same vertical level as the select transistor, a pass transistor of the plurality of pass transistors being configured to selectively couple a control gate of a respective one of the memory cells to a corresponding global access line of a plurality of global access lines.

A memory device, comprising:

• a plurality of substantially vertical strings of series-coupled memory cells, the memory cells in each string of series-coupled memory cells of the plurality of substantially vertical strings of series-coupled memory cells respectively at different vertical levels;
• a plurality of access plates respectively at substantially the different vertical levels of the memory cells in each string of series-coupled memory cells of the plurality of substantially vertical strings of series-coupled memory cells, the memory cells at each of the different vertical levels commonly coupled to the access plate at substantially that vertical level;
• a plurality of select plates at a vertical level above a vertical level of a top access plate of the plurality of access plates;
• a plurality of data lines at a vertical level above the vertical level of the plurality of select plates;
• a plurality of select transistors commonly coupled to each of the data lines of the plurality of data lines so that the select transistors commonly coupled to each of the data lines of the plurality of data lines are coupled to respective ones of the plurality of select plates, wherein each of the plurality of select transistors commonly coupled to each of the data lines of the plurality of data lines is configured to selectively couple that data line to a respective one of the strings of series-coupled memory cells;
• a pass-gate plate at substantially the same vertical level as the plurality of select plates;
• and
• a plurality of vertical pass transistors passing through and commonly coupled to the pass-gate plate, each of the plurality of vertical pass transistors being configured to selectively couple a respective one of the access plates to a respective one of a plurality of global access lines;
• wherein the plurality of vertical pass transistors are at substantially the same vertical level as the pass-gate plate and the plurality of select transistors are at substantially the same vertical level as the plurality of select plates.

A method of forming a memory device, comprising:

• forming a stack of tiers of memory cells;
• forming a tier of local devices at a level above the stack of tiers of memory cells;
• forming a tier of global devices at substantially a same level as the tier of local devices substantially concurrently with forming the tier of local devices;
• wherein a local device of the tier of local devices provides selective access to a data line;
• wherein a global device of the tier of global devices provides selective access to a global access line;
• and
• wherein a tier of memory cells of the stack of tiers of memory cells is configured to be selectively coupled to the global access line by the global device of the tier of global devices.

A method of forming a memory device, comprising:

• forming a plurality of stacked memory cells respectively at different vertical levels;
• forming a select transistor above the plurality of stacked memory cells, the select transistor configured to selectively couple the plurality of stacked memory cells to a data line;
• and
• forming a plurality of pass transistors at substantially the same vertical level as the select transistor and substantially concurrently with forming the select transistor, a pass transistor of the plurality of pass transistors being configured to selectively couple a control gate of a respective one of the memory cells to a corresponding global access line of a plurality of global access lines.

A method of forming a memory device, comprising:

• forming a plurality of access plates;
• forming a plurality of substantially vertical strings of series-coupled memory cells, the memory cells in each string of series-coupled memory cells of the plurality of substantially vertical strings of series-coupled memory cells respectively at different vertical levels, the access plates of the plurality of access plates respectively at substantially the different vertical levels of the memory cells in each string of series-coupled memory cells of the plurality of substantially vertical strings of series-coupled memory cells, the memory cells at each of the different vertical levels commonly coupled to the access plate at substantially that vertical level;
• forming a plurality of select plates and a pass-gate plate substantially concurrently at a vertical level above a vertical level of a top access plate of the plurality of access plates;
• forming a plurality of select transistors and a plurality of pass transistors substantially concurrently at substantially the vertical level of the plurality of select plates and the pass-gate plate;
• and
• forming a plurality of data lines and a plurality of global access lines substantially concurrently at a vertical level above the vertical level of the plurality of select plates and the plurality of pass transistors;
• wherein select transistors of the plurality of select transistors are commonly coupled to each of the data lines of the plurality of data lines;
• wherein the select transistors of the plurality of select transistors that are commonly coupled to each of the data lines of the plurality of data lines are coupled to respective ones of the plurality of select plates;
• wherein each of the plurality of select transistors commonly coupled to each of the data lines of the plurality of data lines is configured to selectively couple that data line to a respective one of the strings of series-coupled memory cells;
• and
• wherein the plurality of pass transistors are commonly coupled to the pass-gate plate, each of the plurality of pass transistors being configured to selectively couple a respective one of the access plates to a respective one of the plurality of global access lines.