Core memory with improved sense-inhibit recovery time

A three wire three dimensional core memory comprising:

• a plurality of mats, each including an array of at least 2048 magnetic memory cores and providing memory for one bit position of a multibit addressed memory word;
• a plurality of drive conductors coupled to selectively switch one core in each mat at an addressed memory location;
• a pair of sense-inhibit conductors for each mat, the two conductors of each pair being connected together at one end and inductively coupled to an approximately equal number of cores from the mat, the conductors being in close physical proximity to each other at at least one point intermediate the mat equidistant along the conductors from the point of connection together and being inductively coupled to cores on each side of the point of close proximity;
• a plurality of electronic circuits, each being connected between a pair of sense-inhibit conductors at a point of close proximity and blocking the communication thereacross of components of differential core switching signals below a threshold magnitude sufficient to permit the detection of core switching signals on the sense-inhibit conductors while permitting the communication thereacross of components of differential signals greater than the threshold magnitude;
• and
• a plurality of sensing circuits, each sensing circuit being connected to sense differential core switching signals appearing across a different pair of conductors at the ends thereof opposite the point of connection.

A core memory stack comprising:

• an array of magnetic storage elements;
• drive conductors inductively coupled to selectively switch magnetic storage elements in the array;
• a pair of sense-inhibit conductors, each inductively coupling approximately half of the storage elements in the array;
• and
• at least one threshold signal level transmission line discontinuity element electrically connected to both of the sense-inhibit conductors at a position therealong intermediate the array and appearing as a transmission line discontinuity to voltage signals in excess of the threshold but having substantially no effect on storage element induced switching signals less than the threshold.

A core memory comprising:

• a plurality of magnetic cores;
• a drive system inductively coupled to drive first selected cores with magnetimotive forces of sufficient magnitude to induce switching;
• a pair of sense-inhibit conductors inductively coupled to selectively oppose the switching of first selected cores and generate a differential voltage across a pair of terminals of the pair of sense-inhibit conductors in response to the switching of a first selected core;
• a current driver, connected to selectively drive first terminals of the pair of sense-inhibit conductors with substantially equal parallel currents;
• a differential sense amplifier coupled to sense differential voltages across terminals of the pair of sense-inhibit conductors and generate an output signal indicative thereof;
• and
• a non-linear electrical circuit electrically disposed intermediate the cores and interconnecting the pair of sense-inhibit conductors at approximately equal distances along the conductors from the first terminals thereof, the electrical circuit appearing as an open circuit to differential voltage signals below a threshold value sufficient to permit sensing of an output signal generated by the switching of a core and appearing as a substantially short circuit between the sense-inhibit conductors to differential voltages greater than the threshold.

A core memory comprising:

• an array of magnetic cores which are switchable between stable states of magnetization;
• a plurality of drive conductors inductively coupled to selectively switch cores in the array between stable states of magnetization;
• first and second sense-inhibit conductors, each being inductively coupled to approximately half of the cores in the array, the first and second sense-inhibit conductors being coupled to carry approximately balanced current for inhibiting the switching of a core in the array and subsequently to carry a differential voltage therebetween which is induced by the switching of a core inductively coupled to a sense-inhibit conductor;
• means for sensing coupled to sense core switching signals induced differentially between the first and second sense-inhibit conductors;
• and
• noise reduction circuitry coupled between the first and second sense-inhibit conductors at corresponding positions therealong having magnetic cores disposed between the points of connection of the noise reduction circuitry and the sensing means, the noise reduction circuitry including means for decreasing the time period required to attenuate differential noise signals which are induced on the first and second conductors by the inhibit currents and which interfere with the detection of the switching of a core, to a magnitude which does not prevent the sensing means from sensing core switching signals.

A magnetic core memory comprising:

• at least one array of magnetic cores;
• a differential voltage sensing circuit having differential inputs;
• means for selectively switching the cores in the array;
• means for sensing output voltage signals generated by selectively switched cores, the switching and sensing means including first and second conductors which are inductively coupled to a plurality of cores in the array and which are coupled to differential inputs of the sensing circuit;
• and
• an electrical circuit connected to at least a first of said first and second conductors at a connection point having at least one memory core inductively coupled to the at least a first of said conductors between the connection point and the differential sensing circuit, the electrical circuit including means for interfering with the passage along the conductor past the connection point of large magnitude signals relative to a similar point on the other conductor of the first and second conductors having approximately the same number of memory cores between the similar point and the differential sensing circuit without substantial interference with the subsequent passage of a differential signal induced on the conductor by the switching of a magnetic core.