Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines

A memory including memory elements arranged in a three-dimensional pattern and with a plurality of parallel planes stacked in a vertical direction, the memory further comprising:

• a plurality of first conductive lines elongated in the vertical direction through the plurality of planes and arranged in a two-dimensional rectangular array in first and second directions,
• a plurality of second conductive lines elongated in the first direction across individual planes and spaced apart in the second direction between and separated from the first plurality of conductive lines in the individual planes, wherein the first and second conductive lines cross adjacent each other at a plurality of locations across the individual planes,
• a plurality of non-volatile re-programmable memory elements elongated in the vertical direction through the plurality of planes and individually connected between the first and second conductive lines adjacent the crossings thereof at the plurality of locations, and
• a plurality of select devices arranged to individually access selected ones of the plurality of non-volatile re-programmable memory elements via selected ones of the plurality of first conductive lines connected to selected ones of a plurality of third conductive lines.

A method of forming a three-dimensional array of re-programmable non-volatile memory elements on a semi-conductor substrate, comprising:

• forming a first set of circuits in the semi-conductor substrate,
• thereafter forming a plurality of planes on top of each other and on top of the substrate, individual planes being formed by a dielectric layer with an electrically conductive layer thereover,
• forming a plurality of parallel trenches through the dielectric and conductive layers of the plurality of planes and to the substrate in a single etch operation, wherein the conductive layers of the planes are separated into first electrically conductive lines extending between the trenches and with edges thereof making up portions of opposing sidewalls of the trenches,
• forming layers of non-conductive re-programmable non-volatile memory material continuously along opposing sidewalls of the trenches including in contact with the edges of the first conductive lines, and
• thereafter forming a plurality of second conductive lines within the trenches between and in contact with the opposing sidewall layers of memory material and spaced apart from each other along the trench, the second conductive lines additionally being formed to extend away from contact with the first set of circuits in the substrate and continuously through the plurality of planes,
• wherein the three-dimensional array of re-programmable non-volatile memory elements is formed in portions of the layers of the memory material positioned between the edges of the first conductive lines and the second conductive lines.