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US 9,251,860 B2Granted
Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods
AssigneeMicron Technology, Inc.
InventorsAaron S. Yip, Mark A. Helm, Ramin Ghodsi
Life of this patent
Estimating the term…
Abstract
In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.
Claims29
A memory device, comprising:
- a stack of tiers of memory cells, wherein each tier of memory cells comprises a plurality of local access lines and a plurality of data lines that cross the plurality of local access lines so that a memory cell is at each crossing of a data line of the plurality of data lines and a local access line of the plurality of local access lines;
- and
- a plurality of global select devices at substantially a same level as an uppermost tier of the stack of tiers of memory cells;
- wherein a global select device of the plurality of global select devices is configured to selectively couple a global access line to a local access line of the plurality of local access lines of a tier of the stack of tiers of memory cells that is at a level below the uppermost tier of the stack of tiers of memory cells.
1 more element
A memory device, comprising:
- a stacked memory array comprising a plurality of levels of commonly coupled memory cells;
- and
- a periphery adjacent to the stacked memory array, the periphery comprising a plurality of global select devices at a level above an uppermost level of the plurality of levels commonly coupled memory cells;
- wherein a global select device of the plurality of global select devices is configured to selectively couple a respective one of the plurality of levels of commonly coupled memory cells to a global access line in the periphery.
1 more element
A memory device, comprising:
- a stacked memory array comprising a plurality of levels of commonly coupled memory cells;
- and
- a plurality of commonly coupled first pass transistors at a level above an uppermost level of the plurality of levels commonly coupled memory cells, wherein a first pass transistor of commonly coupled first pass transistors is coupled to a respective one of the plurality of levels of commonly coupled memory cells;
- and
- a plurality of commonly coupled second pass transistors at substantially a same level as the plurality of commonly coupled first pass transistors, wherein a second pass transistor of the plurality of commonly coupled second pass transistors is coupled to one of a plurality of lines that are at a level below the stacked memory array, and is coupled in series with the first pass transistor that is coupled to the respective one of the plurality of levels of commonly coupled memory cells.
2 more elements
A memory device, comprising:
- a stacked memory array comprising a plurality of levels of commonly coupled memory cells;
- a plurality of commonly coupled select transistors at a level below a lowermost level of the plurality of levels of commonly coupled memory cells, wherein a select transistor of the plurality of commonly coupled select transistors is configured to selectively couple a string of memory cells comprising one memory cell from each of plurality of levels of commonly coupled memory cells to a source that is at a level below the level of the plurality of commonly coupled select transistors;
- a plurality of commonly coupled first pass transistors at a level above an uppermost level of the plurality of levels commonly coupled memory cells, wherein a first pass transistor of commonly coupled first pass transistors is coupled to the commonly coupled select transistors;
- and
- a plurality of commonly coupled second pass transistors at substantially a same level as the plurality of commonly coupled first pass transistors, wherein a second pass transistor of the plurality of commonly coupled second pass transistors is coupled to one of a plurality of lines that are at a level below the source.
2 more elements
A memory device, comprising:
- a stacked memory array comprising a plurality of levels of commonly coupled memory cells;
- a plurality of commonly coupled first select transistors at a level below a lowermost level of the plurality of levels of commonly coupled memory cells, wherein a first select transistor of the plurality of commonly coupled first select transistors is configured to selectively couple a string of memory cells comprising one memory cell from each of plurality of levels of commonly coupled memory cells to a source that is at a level below the level of the plurality of commonly coupled select transistors;
- a second select transistor at a level above an uppermost level of the plurality of levels of commonly coupled memory cells, wherein the second select transistor is configured to couple the string of memory cells to a data line that is above the second select transistor;
- and
- a plurality of commonly coupled pass transistors at substantially level of the second select transistor, wherein a pass transistor of the commonly coupled pass transistors is coupled to a global access line that is below the source and to the second select transistor.
2 more elements
Dependencies are inferred from the claim text.