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US 2017/0004881 A1Published application
Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines and a Single-Sided Word Line Architecture
AssigneeSanDisk Technologies LLC
InventorsTianhong Yan, George Samachisa
Life of this patent
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Abstract
A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
Claims18
A data memory, comprising:
- a plurality of non-volatile re-programmable memory elements arranged in a three dimensional pattern defined by rectangular coordinates along x, y and z directions and with a plurality of parallel planes stacked in the z direction on top of a semiconductor substrate;
- a plurality of first conductive lines elongated in the z direction through the plurality of planes and arranged in a two dimensional rectangular array of rows in the x direction and columns in the y-direction;
- a plurality of second conductive lines elongated in the x-direction across each of the planes and spaced apart in they-direction between and separated from the first plurality of conductive lines in each of the planes, wherein the first and second conductive lines cross adjacent each other at a plurality of locations across each of the planes, the plurality of second conductive lines forming pairs of adjacent second conductive lines, wherein each non-volatile re-programmable memory element is connected between a corresponding first conductive line and a corresponding second conductive line crossing each other at an associated location of the plurality of locations;
- and
- a plurality of select devices arranged to individually couple a selected row of first conductive lines to respective sensing circuits via a plurality of third conductive lines,
- wherein, for each of the pairs of adjacent second conductive lines, each second conductive line is connected to only one corresponding row of first conductive line such that both of the second conductive lines of each pair are connected to the same row of first conductive lines and such that each connection made with each first conductive line of the corresponding row of first conductive lines is via a single corresponding non-volatile re-programmable memory element, and
- wherein each memory element is positioned between a respective first conductive line and a respective second conductive line, and is in the plane of said plurality of planes where said respective second conductive line is placed, to contact the first conductive line in the y-direction.
4 more elements
A method of operating a re-programmable non-volatile memory system, comprising:
- utilizing at least one integrated circuit that includes a three-dimensional pattern of memory elements defined by rectangular coordinates along x, y and z-directions and which includes:
- a plurality of parallel planes stacked in the z-direction on top of a semiconductor substrate,
- a plurality of conductive local bit lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of rows in the x and columns in they-directions,
- a plurality of word lines elongated in the x-direction across each of the planes and spaced apart in they-direction between and separated from the plurality of local bit lines in each of the planes, wherein the local bit lines and word lines cross adjacent each other at a plurality of locations across each of the planes, the plurality of word lines forming pairs of adjacent word lines,
- a plurality of re-programmable non-volatile memory elements, each non-volatile re-programmable memory element being connected between a corresponding local bit line and a corresponding word line crossing each other at an associated location of the plurality of locations, and
- a plurality of select devices arranged to individually couple a selected row of local bit lines to respective sensing circuits via a plurality of global bit lines in response to a select control signal;
- applying said select control signal to the plurality of select devices in order to connect the selected row of local bit lines to individual ones of the global bit lines;
- and
- causing a selected one or more of the plurality of memory elements to simultaneously change between at least first and second states by applying one of first and second stimuli through one or more of the plurality of word lines and global bit lines between which the selected one or more of the plurality of memory elements are operably connected,
- wherein, for each of the pairs of adjacent word lines, each word line is connected to only one corresponding row of local bit lines, such that both of the word lines of each pair are connected to the same row of local bit lines and such that each connection made with each local bit line of the corresponding row of local bit lines is via a single corresponding non-volatile re-programmable memory element, and
- wherein each memory element is positioned between a respective local bit line and a respective word line to contact the respective local bit line in the y-direction.
8 more elements
Dependencies are inferred from the claim text.