Ferromagnetic memory device

A ferromagnetic memory cell comprising:

• a substrate having a surface;
• a transistor having a first current electrode formed within the substrate and exposed at the surface of the substrate, a second current electrode formed within the substrate and exposed at the surface of the substrate, and a control electrode which lies substantially between the first current electrode and the second current electrode and controls current flow between the first current electrode and the second current electrode;
• a ferromagnetic region overlying the substrate and positioned in close proximity to the transistor;
• an opening formed in the ferromagnetic region;
• and
• a first conductive region formed within the opening in the ferromagnetic region, the first conductive region being electrically coupled to the first current electrode.

An integrated circuit having a plurality of memory cells, each memory cell within the plurality of memory cells comprising:

• a substrate portion;
• a transistor having an electrode overlying the substrate portion;
• a conductive element connected to the electrode, the conductive element overlying the substrate portion;
• and
• a ferromagnetic core coupled to the conductive element wherein the magnetic energy in the ferromagnetic core is changed by current through the ferromagnetic core, the ferromagnetic core overlying the substrate portion.

A memory cell comprising:

• a transistor having an electrode;
• a dielectric layer overlying the transistor and having an opening which exposes the electrode;
• a conductive element connected to the electrode;
• and
• a ferromagnetic core formed in close proximity to the conductive element so that the ferromagnetic core is electrically coupled to the conductive element wherein the magnetic energy in the ferromagnetic core is selectively changed by a current flowing through the conductive element, the ferromagnetic core overlying the dielectric layer.

An integrated circuit memory cell comprising:

• a semiconductor substrate;
• a transistor device formed within the semiconductor substrate;
• a dielectric layer overlying the transistor device;
• an annular ferromagnetic core overlying the dielectric layer and being coupled to the transistor device.

A ferromagnetic memory circuit comprising:

• a power supply conductor;
• a transistor having a first current electrode, a second current electrode for receiving a power supply voltage from the power supply conductor, and a control electrode;
• a ferromagnetic core formed directly overlying a portion of the transistor and being encapsulated in a dielectric layer;
• and
• a conductor passing adjacent to the ferromagnetic core and being coupled to the first current electrode of said transistor, the conductor selectively affecting a magnetic field within the ferromagnetic core.

A ferromagnetic memory cell comprising:

• a transistor having a first current electrode, a second current electrode, and a control electrode which lies substantially between the first current electrode and the second current electrode and controls current flow between the first current electrode and the second current electrode;
• a ferromagnetic region positioned adjacent the transistor and being at least partially surrounded by a dielectric layer;
• and
• a first conductive region formed adjacent the ferromagnetic region, the first conductive region being electrically coupled to the first current electrode.

An integrated circuit wherein the integrated circuit has a plurality of magnetic memory devices formed on a substrate, one magnetic memory device comprising:

• only one single transistor;
• a ferromagnetic core in close proximity to the only one single transistor;
• a conductor coupled to the transistor and being positioned close enough to the ferromagnetic core to allow the ferromagnetic core to store a logic value selected from a group consisting of:
• a logic one and a logic zero, in response to a current flow through the conductor.

A semiconductor magnetic memory device comprising:

• a substrate;
• a transistor formed from the substrate and having a first current electrode overlying the substrate, a second current electrode overlying the substrate and being separated from the first current electrode by a channel region, and a gate electrode which overlies the channel region;
• a first dielectric layer formed overlying the transistor;
• a ferromagnetic region formed overlying the first dielectric layer, the ferromagnetic region having a sidewall;
• a second dielectric layer formed overlying the ferromagnetic region;
• and
• a first conductive region formed adjacent the sidewall of the ferromagnetic region.