Integrated circuit memory devices having resistive memory cells therein and methods of operating same

A method of operating a resistive memory device including a memory cell array having a plurality of resistive memory cells therein, comprising:

• receiving a write command from an external memory controller;
• receiving an address and a data from the external memory controller;
• performing a reset write operation on a target page by applying a ground voltage to a first word-line, wherein each of the resistive memory cells in the target page includes a variable resistor element coupled to each of source lines and two selection transistors having different conductivity types, the two selection transistors being coupled in parallel to each of the source lines, a first word-line and each of bit-lines, each of the source lines being coupled to the column decoder and write drivers;
• and
• performing a set write operation on a portion of the target page by applying a power supply voltage to the first word-line based on the data.

A nonvolatile resistive memory device, comprising:

• an array of resistive memory cells having respectively pluralities of word, bit and source lines connected thereto;
• row and column decoders, and a control circuit coupled to the row and column decoders;
• and
• a write/read circuit coupled to the column decoder and the control circuit, the write/read circuit configured to perform a write operation that transfers write data into a target page of resistive memory cells within the array;
• wherein a first resistive memory cell within the array includes:
• a variable resistor element having a first terminal coupled to a first source line within the plurality thereof;
• and
• first and second selection transistors configured in combination as a CMOS transmission gate having a first current carrying terminal coupled to a first bit line within the plurality thereof, a second current carrying terminal coupled to a second terminal of the variable resistor element, and a gate control terminal coupled to a first word line within the plurality thereof;
• and
• wherein a first write driver within the write/read circuit is configured to perform a set write operation on the variable resistor element using the first selection transistor within the CMOS transmission gate to establish a first current path in a first direction through the variable resistor element, and perform a reset write operation on the variable resistor element using the second selection transistor within the CMOS transmission gate to establish a second current path in a second direction through the variable resistor element, which is opposite the first direction.