G06F 9/38585
With result invalidation
Official title: {with result invalidation, e.g. nullification}
G06F9/38585 (With result invalidation) appears on 481 US grants and 479 published applications in this corpus.
Search patents in G06F- Granted patents
- 481
- Published applications
- 479
- Assignees
- 95
- Inventors
- 811
- Latest grant
- 18 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1986 | 1 | 0 |
| 1987 | 1 | 0 |
| 1988 | 1 | 0 |
| 1989 | 0 | 0 |
| 1990 | 1 | 0 |
| 1991 | 1 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 2 | 0 |
| 1995 | 3 | 0 |
| 1996 | 2 | 0 |
| 1997 | 3 | 0 |
| 1998 | 5 | 0 |
| 1999 | 11 | 0 |
| 2000 | 13 | 0 |
| 2001 | 10 | 1 |
| 2002 | 10 | 12 |
| 2003 | 9 | 7 |
| 2004 | 12 | 11 |
| 2005 | 10 | 12 |
| 2006 | 12 | 15 |
| 2007 | 7 | 23 |
| 2008 | 16 | 19 |
| 2009 | 13 | 20 |
| 2010 | 18 | 14 |
| 2011 | 21 | 13 |
| 2012 | 9 | 15 |
| 2013 | 15 | 27 |
| 2014 | 9 | 21 |
| 2015 | 14 | 31 |
| 2016 | 45 | 55 |
| 2017 | 26 | 58 |
| 2018 | 46 | 30 |
| 2019 | 39 | 22 |
| 2020 | 29 | 14 |
| 2021 | 20 | 12 |
| 2022 | 13 | 14 |
| 2023 | 13 | 11 |
| 2024 | 12 | 6 |
| 2025 | 4 | 9 |
| 2026 | 5 | 7 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Performing memory dependency identification without previously encountered read-after-write (RAW) hazards in processor devices18 Aug 2026US 12,710,962 B2QUALCOMM Incorporated
- Processing of synchronization barrier instructions26 May 2026US 12,639,070 B2Apple Inc.
- Data processing systems and methods for controlling storage of input data values for use by an executing unit17 Feb 2026US 12,554,492 B2Arm Limited
- Processing for processors performing tasks having forward conditional branch instructions3 Feb 2026US 12,541,367 B2Microsoft Technology Licensing, LLC
- Mixed-sourced dependency control for vector instructions6 Jan 2026US 12,517,734 B2Akeana, Inc.
- Responsiveness when looping on speculative atomic memory updates25 Jun 2026US 2026/0178430 A1International Business Machines Corporation
- Method and apparatus for pipeline inclusion tracking11 Jun 2026US 2026/0161408 A1Intel Corporation
- Systems, methods, and apparatuses for heterogeneous computing11 Jun 2026US 2026/0161441 A1Intel Corporation
- Processing Vector Instructions23 Apr 2026US 2026/0111231 A1
- Performing "cold" memory dependency identification in processor devices12 Mar 2026US 2026/0072686 A1QUALCOMM Incorporated
Most cited
By later US patents
- Method and apparatus for debugging an integrated circuit172US 6,499,123 B1Advanced Micro Devices, Inc. · 2002
- Data processor for concurrent executing of instructions by plural execution units157US 4,942,525 AHitachi, Ltd. · 1990
- Method and system for programmable pipelined graphics processing with branching instructions148US 6,947,047 B1NVIDIA Corporation · 2005
- Method and apparatus for releasing memory locations during transactional execution110US 7,206,903 B1Sun Microsystems, Inc. · 2007
- Controlling priority levels of pending threads awaiting processing103US 8,589,934 B2Arm Limited · 2013