Processing of synchronization barrier instructions

A method, comprising:

• during execution of an instruction synchronization barrier (ISB) instruction by a processor:
• initiating fetching of a younger instruction prior to retirement of one or more older instructions, wherein the one or more older instructions are before the ISB instruction in program order and the younger instruction is after the ISB instruction in the program order, and wherein the one or more older instructions update data in one or more registers;
• and
• responsive to retirement of the one or more older instructions, retiring the ISB instruction without flushing the younger instruction responsive to determining that the younger instruction does not the data in the one or more registers updated by the one or more older instructions.

A device, comprising:

• a processor;
• and
• memory storing program instructions including an instruction synchronization barrier (ISB) instruction executable by the processor,
• wherein during execution of the ISB instruction, the processor is configured to:
• initiate fetching of a younger instruction prior to retirement of one or more older instructions, wherein the one or more older instructions are before the ISB instruction in program order and the younger instruction is after the ISB instruction in the program order, and wherein the one or more older instructions update data in one or more registers;
• and
• responsive to retirement of the one or more older instructions, retire the ISB instruction without flushing the younger instruction responsive to determining that the younger instruction does not access the data in the one or more registers updated by the one or more older instructions.