Data processor for concurrent executing of instructions by plural execution units
AssigneeHitachi, Ltd.
InventorsYooichi Shintani, Kazunori Kuriyama, Tohru Shonai, Eiki Kamada, Kiyoshi Inoue
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AssigneeHitachi, Ltd.
InventorsYooichi Shintani, Kazunori Kuriyama, Tohru Shonai, Eiki Kamada, Kiyoshi Inoue
Estimating the term…
An information processing apparatus in which instructions are processed one by one conceptually and results thereof are conceptually orderly written into a memory comprises an instruction control circuit capable of decoding M instructions and reading operands in parallel, N (N.gtoreq.M) execution circuits capable of executing a plurality of instructions mutually in parallel, a detection circuit for determining whether all of M execution circuits of the N execution circuits required by the M instructions decoded by the instruction control circuit are vacant or not, and a reserve circuit for reserving the execution of the M decoded instruction while the detection fails to detect sufficient vacancy.
An information processing apparatus for executing sequentially-ordered instructions, which apparatus requires suppression of the execution of a subset of the sequentially ordered instructions, said subset including those instructions succeeding, in the sequential order, one of the sequentially ordered instructions when a predetermined result for an interrupt is generated as a result of execution of the one instruction, comprising:
An information processing apparatus including a storage device for executing sequentially ordered instructions which apparatus requires suppression of the execution of a subset of the sequentially-ordered instructions succeeding, in the sequential order, one of the sequentially-ordered instructions when a predetermined result for an interrupt is generated as a result of execution of the one instruction, comprising:
Dependencies are inferred from the claim text.