Method and system for programmable pipelined graphics processing with branching instructions

A programmable graphics processor operable in any one of a parallel processing mode and a serialized mode, said processor comprising:

• input buffers;
• output buffers;
• at least three processing pipelines connected between the input buffers and the output buffers, including a first pipeline, a second pipeline, and a third pipeline, wherein each of the pipelines is configured to process data in accordance with a program including by executing branch instructions;
• and
• mode control circuitry coupled and configured to receive instructions for pipelined execution of the program, assert the instructions to the pipelines, monitor the instructions at least in the parallel processing mode to identify each branch instruction of the instructions before execution of the branch instruction in any of the pipelines, and cause the processor to operate in the serialized mode when necessary to prevent any conflict between the pipelines due to branching, wherein
• in the parallel processing mode, data values launched from the input buffers into the first pipeline, the second pipeline, and the third pipeline during a clock cycle are processed in parallel in the first pipeline, the second pipeline, and the third pipeline in accordance with the program and by executing identical instructions, and
• in the serialized mode, each data value launched into one of the pipelines is processed in said one of the pipelines while operation of each other one of the pipelines is frozen.

A graphics processing system, including:

• a programmable vertex processor operable in any one of a parallel processing mode and a serialized mode to generate vertex data;
• a rasterizer coupled to receive the vertex data from the vertex processor and configured to generate rendered data in response to the vertex data;
• and
• a pixel processor coupled to receive the rendered data from the rasterizer and configured to perform at least one of a texturing operation and a color changing operation on the rendered data,
• wherein the vertex processor includes:
• at least two processing pipelines, wherein each of the pipelines is configured to process data in accordance with a program, including by executing branch instructions;
• and
• mode control circuitry coupled and configured to receive instructions for pipelined execution of the program, to assert the instructions to the pipelines, to monitor the instructions at least in the parallel processing mode to identify each branch instruction of the instructions before execution of the branch instruction in any of the pipelines, and to cause the vertex processor to operate in the serialized mode when necessary to prevent any conflict between the pipelines due to branching, wherein
• in the parallel processing mode, data values are launched into N of the pipelines during one clock cycle, where N≧2, and the data values are processed in parallel in said N of the pipelines in accordance with the program with said N of the pipelines each executing identical instructions, and
• in the serialized mode, each data value launched into one of the pipelines is processed in said one of the pipelines while operation of each other one of the pipelines is frozen.

A graphics processing system, including;

• a programmable vertex processor operable in any one of a parallel processing mode and a serialized mode to generate vertex data;
• a rasterizer coupled to receive the vertex data from the vertex processor and configured to generate rendered data in response to the vertex data;
• and
• a pixel processor coupled to receive the rendered data from the rasterizer and configured to perform at least one of a texturing operation and a color changing operation on the rendered data,
• wherein the vertex processor comprises:
• at least two processing pipelines, wherein each of the pipelines is configured to process data in accordance with a program;
• and
• mode control circuitry coupled and configured to receive instructions for pipelined execution of the program, to assert the instructions to the pipelines such that the pipelines receive identical instructions in at least the parallel processing mode, to monitor the instructions at least in the parallel processing mode to identify a conflict-causing instruction before execution of the conflict-causing instruction in any of the pipelines, and to cause the vertex processor to commence operation in the serialized mode to prevent a conflict between the pipelines that would occur during execution of the conflict-causing instruction in the parallel processing mode.

A method for pipelined processing of graphics data in accordance with a program, in at least one of a parallel processing mode and a serialized mode, said method including the steps or:

• (a) monitoring instructions of the program to identify each branch instruction of the program before commencing to execute the branch instruction;
• (b) while performing step (a), executing the program on parallel streams of the data in multiple processing pipelines in the parallel processing mode in single-instruction-multiple-data fashion, at least until a branch instruction is identified in step (a);
• and
• (c) if a branch instruction is identified while performing steps (a) and (b), ceasing execution of the program in the parallel processing mode and completing execution of the program in the serialized mode, if necessary to prevent conflict between the pipelines due to branching.

A method for pipelined processing of graphics data in accordance with a program in at least one of a parallel processing mode and a serialized mode, said method including the steps of:

• (a) monitoring instructions of the program to identify each conflict-causing instruction of the program before commencing to execute the conflict-causing instruction;
• (b) while performing step (a), executing the program on parallel streams of the data in multiple processing pipelines in the parallel processing mode, at least until a conflict-causing instruction is identified in step (a);
• and
• (c) if a conflict-causing instruction is identified while performing steps (a) and (b), halting execution of the program in the parallel processing mode, and executing at least one instruction of the program including the identified conflict-causing instruction in the serialized mode, thereby preventing a conflict between the pipelines that would otherwise occur during execution of the identified conflict-causing instruction in the parallel processing mode.