Controlling priority levels of pending threads awaiting processing

The data processing apparatus comprising:

• processing circuitry configured to process processing threads using resources accessible to said processing circuitry;
• a pipeline for handling at least two pending threads awaiting processing by said processing circuitry, said pipeline comprising at least one pipeline stage including at least one resource-requesting pipeline stage for requesting access to said resources for said pending threads;
• a pipeline controller configured to determine whether requested resources are available for a pending thread in a final pipeline stage of said pipeline, to return said pending thread to a first pipeline stage of said pipeline if said requested resources are not yet available for said pending thread, and to forward said pending thread from said pipeline if said requested resources are available for said pending thread;
• a priority controller for controlling priority levels of said pending threads, said priority levels defining a priority with which respective pending threads are granted access to resources, pending threads being assigned a base priority level when entering said pipeline for the first time;
• wherein said priority controller is configured to selectively raise the current priority level of a pending thread in said final pipeline stage if said pipeline controller returns said pending thread to said first pipeline stage,
• wherein said priority levels are represented by a set of discrete values including a base value representing said base priority level and at least one further value representing at east one higher priority level, wherein said pipeline is configured to handle a maximum of N pending threads, and said set of discrete values comprises M-bit values, where N is an integer and M is the smallest integer greater than or equal to log2(N).

The data processing apparatus comprising:

• processing circuitry configured to process processing threads using resources accessible to said processing circuitry;
• a pipeline for handling at least two pending threads awaiting processing by said processing circuitry, said pipeline comprising at least one pipeline stage including at least one resource-requesting pipeline stage for requesting access to said resources for said pending threads;
• a pipeline controller configured to determine whether requested resources are available for a pending thread in a final pipeline stage of said pipeline, to return said pending thread to a first pipeline stage of said pipeline if said requested resources are not yet available for said pending thread, and to forward said pending thread from said pipeline if said requested resources are available for said pending thread;
• a priority controller for controlling priority levels of said pending threads, said priority levels defining a priority with which respective pending threads are granted access to resources, pending threads being assigned a base priority level when entering said pipeline for the first time,
• wherein said priority controller is configured to selectively raise the current priority level of a pending thread in said final pipeline stage if said pipeline controller returns said pending thread to said first pipeline stage,
• wherein said resources include data or instructions from a cache memory, and at least one of said resource-requesting pipeline stages comprises a cache requesting stage configured to issue to said cache memory cache access requests for data or instructions for a pending thread in said cache requesting stage,
• wherein said cache requesting stage is configured to determine, if a cache access request for a pending thread in said cache requesting stage results in a cache miss, whether said cache memory includes an available storage location, and if said cache memory includes an available storage location to allocate said available cache storage location to said pending thread and trigger a memory access request for data or instructions requested by said cache access request, wherein said cache requesting stage is configured to:
• determine, if said cache memory does not include an available storage location, whether an unavailable cache storage location of said cache memory is allocated to another pending thread having a lower priority than said pending thread in said cache requesting stage, and
• if said unavailable cache storage location is allocated to another pending thread having a lower priority than said pending thread in said cache requesting stage, to re-allocate said unavailable cache storage location to said current pending thread and trigger a memory access request for said data or instructions requested by said cache access request.

A data processing apparatus comprising:

• processing means for processing threads using resources accessible to said processing means;
• pipeline means for handling at least two pending threads awaiting processing by said processing means, said pipeline means comprising at least one pipeline stage means including at least one resource-requesting pipeline stage means for requesting access to said resources for said pending threads;
• pipeline control means for determining whether requested resources are available for a pending thread in a final pipeline stage means of said pipeline means, for returning said pending thread to a first pipeline stage means of said pipeline means if said requested resources are not yet available for said pending thread, and for forwarding said pending thread from said pipeline means if said requested resources are available for said pending thread;
• priority control means for controlling priority levels of said pending threads, said priority levels defining a priority with which respective pending threads are granted access to resources, pending threads being assigned a base priority level when entering said pipeline means for the first time;
• wherein said priority control means is arranged to selectively raise the current priority level of a pending thread in said final pipeline stage means if said pipeline control means returns said pending thread to said first pipeline stage means,
• wherein said priority levels are represented by a set of discrete values including a base value representing said base priority level and at least one further value representing at least one higher priority level, and
• wherein said pipeline means is configured to handle a maximum of N pending threads, and said set of discrete values comprises M-bit values, where M and N are integers and M<log2(N).

A data processing method for an apparatus comprising processing circuitry for processing threads using resources accessible to said processing circuitry and a pipeline for handling at least two pending threads awaiting processing by said processing circuitry, said pipeline comprising at least one pipeline stage including at least one resource-requesting pipeline stage for requesting access to resources for said pending threads, wherein said pending threads are associated with priority levels defining a priority with which respective pending threads are granted access to resources, pending threads being assigned a base priority level when entering said pipeline for the first time;

• the method comprising the steps of:
• (a) determining whether requested resources are available for a pending thread in a final pipeline stage of said pipeline;
• (b) if said requested resources are not yet available for said pending thread in said final pipeline stage, returning said pending thread to a first pipeline stage of said pipeline and selectively raising the current priority level of said pending thread;
• and
• (c) if said requested resources are available for said pending thread in said final pipeline stage, forwarding said pending thread from said pipeline,
• wherein said priority levels are represented by a set of discrete values including a base value representing said base priority level and at least one further value representing at least one higher priority level, and
• wherein said pipeline is configured to handle a maximum of N pending threads, and said set of discrete values comprises M-bit values, where M and N are integers and M<log2(N).