Mixed-sourced dependency control for vector instructions

A computer program product embodied in a non-transitory computer readable medium for instruction execution, the computer program product comprising code which causes one or more processors to generate semiconductor logic for:

• accessing a processor core, wherein the processor core executes instructions from a plurality of categories, wherein the plurality of categories include A-type instructions and B-type instructions, wherein the processor core includes one or more A-type issue queues which are associated with A-type instructions, wherein the processor core includes one or more B-type issue queues which are associated with one or more B-type instructions, wherein an A-type issue queue within the one or more A-type issue queues is communicatively coupled with a B-type issue queue within the one or more B-type issue queues, and wherein the processor core includes one or more dependency content addressable memories (DCAMs);
• associating a DCAM within the one or more DCAMs with an entry of the A-type issue queue, wherein the associating includes a unique temporary register;
• detecting a dependency within an A-type instruction, wherein the dependency is based on an output of a B-type instruction, and wherein the detecting identifies a physical output register ID associated with the B-type instruction;
• dispatching the A-type instruction and the B-type instruction, wherein the A-type instruction is sent to the A-type issue queue and the B-type instruction is sent to the B-type issue queue, wherein the dispatching includes the physical output register ID;
• executing, by the processor core, the B-type instruction;
• snooping a completion bus associated with the B-type issue queue, wherein the snooping is based on the physical output register ID;
• searching, for a match in the DCAM, wherein the searching is based on the physical output register ID that was snooped, wherein the searching causes a hit in the DCAM, and wherein the DCAM returns the unique temporary register that was associated with the DCAM;
• storing, in the unique temporary register that was returned, the output of the B-type instruction, from the completion bus, wherein the storing clears a dependency flag in the A-type issue queue, wherein the clearing indicates that the dependency has been satisfied;
• and
• executing the A-type instruction, wherein the dependency is satisfied with data within the unique temporary register that was returned.

A computer system for instruction execution comprising:

• a memory which stores instructions;
• one or more processors coupled to the memory wherein the one or more processors, when executing the instructions which are stored, are configured to:
• access a processor core, wherein the processor core executes instructions from a plurality of categories, wherein the plurality of categories include A-type instructions and B-type instructions, wherein the processor core includes one or more A-type issue queues which are associated with A-type instructions, wherein the processor core includes one or more B-type issue queues which are associated with one or more B-type instructions, wherein an A-type issue queue within the one or more A-type issue queues is communicatively coupled with a B-type issue queue within the one or more B-type issue queues, and wherein the processor core includes one or more dependency content addressable memories (DCAMs);
• associate a DCAM within the one or more DCAMs with an entry of the A-type issue queue, wherein the associating includes a unique temporary register;
• detect a dependency within an A-type instruction, wherein the dependency is based on an output of a B-type instruction, and wherein the detecting identifies a physical output register ID associated with the B-type instruction;
• dispatch the A-type instruction and the B-type instruction, wherein the A-type instruction is sent to the A-type issue queue and the B-type instruction is sent to the B-type issue queue, wherein the dispatching includes the physical output register ID;
• execute, by the processor core, the B-type instruction;
• snoop a completion bus associated with the B-type issue queue, wherein the snooping is based on the physical output register ID;
• search, for a match in the DCAM, wherein the searching is based on the physical output register ID that was snooped, wherein the searching causes a hit in the DCAM, and wherein the DCAM returns the unique temporary register that was associated with the DCAM;
• store, in the unique temporary register that was returned, the output of the B-type instruction, from the completion bus, wherein the storing clears a dependency flag in the A-type issue queue, wherein the clearing indicates that the dependency has been satisfied;
• and
• execute the A-type instruction, wherein the dependency is satisfied with data within the unique temporary register that was returned.