G06F 9/3854
Instruction completion
Official title: {Instruction completion, e.g. retiring, committing or graduating}
G06F9/3854 (Instruction completion) appears on 2,702 US grants and 2,192 published applications in this corpus.
Search patents in G06F- Granted patents
- 2,702
- Published applications
- 2,192
- Assignees
- 343
- Inventors
- 3,350
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 1 | 0 |
| 1987 | 1 | 0 |
| 1988 | 2 | 0 |
| 1989 | 2 | 0 |
| 1990 | 3 | 0 |
| 1991 | 6 | 0 |
| 1992 | 7 | 0 |
| 1993 | 9 | 0 |
| 1994 | 15 | 0 |
| 1995 | 25 | 0 |
| 1996 | 51 | 0 |
| 1997 | 69 | 0 |
| 1998 | 118 | 0 |
| 1999 | 117 | 0 |
| 2000 | 93 | 0 |
| 2001 | 94 | 13 |
| 2002 | 72 | 50 |
| 2003 | 66 | 61 |
| 2004 | 54 | 94 |
| 2005 | 60 | 62 |
| 2006 | 62 | 66 |
| 2007 | 73 | 83 |
| 2008 | 63 | 93 |
| 2009 | 62 | 67 |
| 2010 | 79 | 56 |
| 2011 | 90 | 55 |
| 2012 | 45 | 54 |
| 2013 | 57 | 82 |
| 2014 | 43 | 93 |
| 2015 | 59 | 98 |
| 2016 | 136 | 160 |
| 2017 | 120 | 191 |
| 2018 | 154 | 123 |
| 2019 | 155 | 135 |
| 2020 | 139 | 109 |
| 2021 | 132 | 97 |
| 2022 | 105 | 79 |
| 2023 | 85 | 80 |
| 2024 | 75 | 74 |
| 2025 | 57 | 58 |
| 2026 | 43 | 59 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- System and method for persisting hardware transactional memory transactions to persistent memory6 Oct 2026US 12,754,842 B1
- Systems, methods, and apparatuses for heterogeneous computing29 Sep 2026US 12,748,618 B2Intel Corporation
- Register allocation decision8 Sep 2026US 12,730,647 B2Arm Limited
- Method and apparatus for permuting streamed data elements8 Sep 2026US 12,730,758 B2Texas Instruments Incorporated
- Lightweight out of order scheduler for processing units25 Aug 2026US 12,717,584 B2The Trustees of Princeton University
- Encoding and Decoding Variable Length Instructions8 Oct 2026US 2026/0310465 A1Imagination Technologies Limited
- Information processing device, information processing system, and information processing method1 Oct 2026US 2026/0300191 A1Hitachi, Ltd.
- Instruction conversion method and processor17 Sep 2026US 2026/0277611 A1Shanghai Zhaoxin Semiconductor Co., Ltd.
- Limited out-of-order execution for matrix instructions17 Sep 2026US 2026/0277615 A1QUALCOMM Incorporated
- Limited out-of-order execution for matrix instructions17 Sep 2026US 2026/0277616 A1QUALCOMM Incorporated
Most cited
By later US patents
- System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling448US 5,179,702 ASupercomputer Systems Limited Partnership · 1993
- Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags403US 5,226,126 ANexgen Microsystems · 1993
- Method and apparatus for user side scheduling in a multiprocessor operating system program that implements distributive scheduling of processes323US 6,195,676 B1Silicon Graphics, Inc. · 2001
- High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations320US 5,651,125 AAdvanced Micro Devices, Inc. · 1997
- System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache299US 5,136,697 AAdvanced Micro Devices, Inc. · 1992