G06F 9/3856
Reordering of instructions
Official title: {Reordering of instructions, e.g. using queues or age tags}
G06F9/3856 (Reordering of instructions) appears on 1,303 US grants and 991 published applications in this corpus.
Search patents in G06F- Granted patents
- 1,303
- Published applications
- 991
- Assignees
- 221
- Inventors
- 1,904
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1988 | 1 | 0 |
| 1989 | 1 | 0 |
| 1990 | 2 | 0 |
| 1991 | 3 | 0 |
| 1992 | 4 | 0 |
| 1993 | 5 | 0 |
| 1994 | 7 | 0 |
| 1995 | 13 | 0 |
| 1996 | 34 | 0 |
| 1997 | 47 | 0 |
| 1998 | 78 | 0 |
| 1999 | 81 | 0 |
| 2000 | 56 | 0 |
| 2001 | 48 | 6 |
| 2002 | 39 | 21 |
| 2003 | 28 | 29 |
| 2004 | 21 | 37 |
| 2005 | 29 | 17 |
| 2006 | 25 | 17 |
| 2007 | 26 | 37 |
| 2008 | 16 | 34 |
| 2009 | 26 | 31 |
| 2010 | 29 | 22 |
| 2011 | 23 | 6 |
| 2012 | 19 | 16 |
| 2013 | 10 | 16 |
| 2014 | 9 | 22 |
| 2015 | 19 | 34 |
| 2016 | 41 | 79 |
| 2017 | 42 | 99 |
| 2018 | 74 | 58 |
| 2019 | 78 | 91 |
| 2020 | 83 | 67 |
| 2021 | 80 | 57 |
| 2022 | 63 | 41 |
| 2023 | 41 | 40 |
| 2024 | 52 | 48 |
| 2025 | 28 | 33 |
| 2026 | 22 | 33 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- System and method for persisting hardware transactional memory transactions to persistent memory6 Oct 2026US 12,754,842 B1
- Method and apparatus for permuting streamed data elements8 Sep 2026US 12,730,758 B2Texas Instruments Incorporated
- Lightweight out of order scheduler for processing units25 Aug 2026US 12,717,584 B2The Trustees of Princeton University
- Performing memory dependency identification without previously encountered read-after-write (RAW) hazards in processor devices18 Aug 2026US 12,710,962 B2QUALCOMM Incorporated
- Cached instruction recording for prediction embedding16 Jun 2026US 12,657,030 B2Apple Inc.
- Encoding and Decoding Variable Length Instructions8 Oct 2026US 2026/0310465 A1Imagination Technologies Limited
- Limited out-of-order execution for matrix instructions17 Sep 2026US 2026/0277615 A1QUALCOMM Incorporated
- Limited out-of-order execution for matrix instructions17 Sep 2026US 2026/0277616 A1QUALCOMM Incorporated
- Traffic reordering for lower toggling20 Aug 2026US 2026/0244450 A1Mellanox Technologies, Ltd.
- Apparatus and method for tagged indirect branch tracking (tibt)2 Jul 2026US 2026/0186787 A1
Most cited
By later US patents
- System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling448US 5,179,702 ASupercomputer Systems Limited Partnership · 1993
- Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags403US 5,226,126 ANexgen Microsystems · 1993
- Method and apparatus for user side scheduling in a multiprocessor operating system program that implements distributive scheduling of processes323US 6,195,676 B1Silicon Graphics, Inc. · 2001
- High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations320US 5,651,125 AAdvanced Micro Devices, Inc. · 1997
- Cluster architecture for a highly parallel scalar/vector multiprocessor system255US 5,197,130 ASupercomputer Systems Limited Partnership · 1993