High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations

A superscalar microprocessor comprising:

• an instruction cache for supplying instructions from a computer program including branch instructions, the instruction cache including a branch prediction unit for predicting the outcome of branch instructions thus determining predicted-taken branches which include speculative instructions to be speculatively executed;
• a multiple instruction decoder, coupled to the instruction cache, for decoding multiple instructions in the same microprocessor cycle, said decoder decoding both integer and floating point instructions in the same microprocessor cycle, said decoder dispatching both decoded integer instructions and decoded floating point instructions in the same microprocessor cycle thus providing dispatched instructions;
• a data processing bus coupled to said decoder;
• an integer functional unit coupled to said data processing bus to receive dispatched instructions from the decoder as speculative instructions, said integer functional unit including a plurality of reservation stations for enabling out-of-order instruction execution by said microprocessor, said integer functional unit speculatively executing said speculative instructions when said speculative instructions are integer instructions thus producing speculative results;
• a floating point functional unit coupled to said data processing bus to receive dispatched instructions from the decoder as speculative instructions, said floating point functional unit including a plurality of reservation stations for enabling out-of-order instruction execution by said microprocessor, said floating point functional unit speculatively executing said speculative instructions when said speculative instructions are floating point instructions thus producing speculative results;
• a branch functional unit coupled to said data processing bus for executing branch instructions and for determining if a branch is a mispredicted branch or a correctly predicted branch;
• a common reorder buffer, coupled to said data processing bus, for use by both said integer functional unit and said floating point functional unit to store said speculative results in common storage elements to enable instructions to be processed speculatively and out-of-order, said reorder buffer renaming registers, issuing multiple instructions in a single cycle, retiring multiple instructions in a single cycle, and deallocating speculative results when such speculative results are in a mispredicted branch, said reorder buffer retiring those results whose status changes from speculative to non-speculative as a consequence of being in a correctly predicted branch;
• a common register file coupled to said data processing bus and to said common reorder buffer for storing results which are retired from said common reorder buffer;
• retire logic, coupled to the common register file, for monitoring the status of results in the common reorder buffer to determine when the status of results in the common reorder buffer changes from speculative to non-speculative as a consequence of being in a correctly predicted branch;
• and
• a load/store functional unit coupled to said data processing bus, for use by both said integer functional unit and said floating point functional unit to permit loading and storage of information.