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US 12,717,584 B2Granted
Lightweight out of order scheduler for processing units
AssigneeThe Trustees of Princeton University
InventorsIshita Chaturvedi, Bhargav Reddy Godala, David I. August
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Abstract
A processing unit leverages a decode stage's pool of instructions, thereby expanding available instruction choices and eliminating the need for expensive OoO techniques to identify reordering opportunities. The processing unit introduces instruction reordering by presenting an alternative instruction to the warp scheduler through the existing interface rather than offering the oldest instruction in each warp. The result is a simple and efficient OoO engine that operates predominantly in the processing unit's front end.
Claims29
A processing unit, comprising:
- a front-end including:
- an issue buffer configured to receive instructions;
- a dependence checker circuit configured to receive instructions and detect any read-after-write (RAW), write-after-read (WAR), or write-after-write (WAW) hazards of each instruction;
- and
- an out-of-order (OoO) scheduler operably coupled to the issue buffer and dependence checker circuit, the OoO scheduler configured to select one or more instructions from the issue buffer for later stages;
- wherein the processing unit is configured to check for idempotence in the dependence checker circuit and does not issue non-idempotent instructions until a translation lookaside buffer hit or miss is determined for all prior load instructions.
3 more elements
A processing unit,
- comprising:
- a front-end including:
- an issue buffer configured to receive instructions;
- a dependence checker circuit configured to receive instructions and detect any read-after-write (RAW), write-after-read (WAR), or write-after-write (WAW) hazards of each instruction;
- and
- an out-of-order (OoO) scheduler operably coupled to the issue buffer and dependence checker circuit, the OoO scheduler configured to select one or more instructions from the issue buffer for later stages,
- wherein the processing unit maintains a Warp-WriteBack (WWb) bit-vector and an Instruction Table Empty (ITE) bit vector where each bit corresponds to a warp.
4 more elements
Dependencies are inferred from the claim text.