US 12,754,842 B1 · System and method for persisting hardware transactional memory transactions to persistent memory

Abstract

Persistent Memory, byte-addressable non-volatile memory technologies, offer performance advantages and access similar to Dynamic Random Access Memory while having the persistence of disk. Hardware Transactional Memory support, originally designed for DRAM concurrency control, can corrupt persistent memory transactions due to cache evictions before system failure. Unifying storage and memory on the main-memory bus and accessed directly while using HTM for concurrency control has previously required the additional burden of changes to processors to prevent possible data corruption. The present invention provides a solution for the durability of transactions to persistent memory while using HTM as a concurrency control mechanism, without any changes to processors or cache-coherency mechanisms. The invention includes a software only method and system that provides durability and ordering of HTM transactions to persistent memory. The invention also discloses a back-end memory controller that supports HTM transactions for durability to persistent memory without up-front processor changes.

Claims17

Dependent claims

A method for providing transaction support for concurrent threads to allow programmers to couple Persistent Memory relaxed durability with the isolation of Hardware Transactional Memory (HTM) originally designed for Dynamic Random Access Memory (DRAM) concurrency-control through a multi-phase sections software library, the method comprising:

upon receiving a request for a transaction start, reading a first system counter, creating a transaction log in a Persistent Memory area, persisting the counter to the log and issuing a persistent memory fence, storing the first system counter in volatile memory, initializing a store set, and starting an HTM concurrency section;
and upon receiving a request for a transaction end, reading a second system counter, ending the HTM concurrency section, starting the logging section, reading a third system counter using an atomic load and increment routine, persisting the second system counter, store set, and third system counter to the log, and issuing a persistent memory fence, and notifying a persistent management routine of completion in the durability section.

A system for durably persisting computer processor Hardware Transactional Memory (HTM) originally designed for Dynamic Random Access Memory (DRAM) concurrency-controlled transactions with relaxed durability onto Persistent Memory, the system comprising:

A computer processor with HTM support, wherein an HTM concurrency section is started with a single processor hardware instruction and ended with a single processor hardware instruction;
a Persistent Memory component containing a log area;
an HTM interface component;
a platform wide read time step counter component;
an atomic load and increment component;
a transaction interface component configured to:
upon transaction start, open a log, record, update and save a first system counter to the log and start an HTM concurrency section;
upon transaction end, read a second system counter using the platform wide read time step component, end the HTM concurrency section, record a third system counter, and persist the counters and store set to the log and record the completed log location in the ordering component;
and a persistence management component for relaxed durability configured to:
advance the minimum open transaction counter by monitoring the first system counter of open transactions and completed log location values of completed transactions, when the first system counter transaction is completed, advancing the minimum open transaction counter;
place completed transactions in a logical order based on the transaction's second system counter;
determine the minimum open value as the minimum value from the set of first system counter values from all logs not marked as complete;
copy store sets of completed logs to Persistent Memory locations that have a recorded third system counter value greater than the minimum open value.

10 more elements

Dependencies are inferred from the claim text.

System and method for persisting hardware transactional memory transactions to persistent memory

Life of this patent

System and method for persisting hardware transactional memory transactions to persistent memory

Life of this patent

Abstract

Claims17