Performing memory dependency identification without previously encountered read-after-write (RAW) hazards in processor devices

A method for performing “cold” memory dependency identification in processor devices, the method comprising:

• detecting, by a dependency identifier circuit of a processor device, a first store instruction in a front end of an instruction processing circuit of the processor device, wherein the first store instruction comprises:
• a single store address register number mapped to a store physical register number;
• and
• a store immediate value;
• writing, by the dependency identifier circuit, the store physical register number, the store immediate value, and an age indicator in an entry of a plurality of entries of a store instruction queue;
• subsequently detecting, by the dependency identifier circuit, a first load instruction in the front end of the instruction processing circuit, wherein the first load instruction comprises:
• a first single load address register number mapped to a first load physical register number;
• and
• a first load immediate value;
• determining, by the dependency identifier circuit, that a first one or more entries of the store instruction queue store the first load physical register number and the first load immediate value;
• responsive to determining that the first one or more entries of the store instruction queue store the first load physical register number and the first load immediate value:
• selecting, by the dependency identifier circuit, an entry of the first one or more entries;
• and
• establishing, by the dependency identifier circuit, a dependency between the first load instruction and a store instruction corresponding to the selected entry;
• detecting, by the dependency identifier circuit, a second load instruction in the front end of the instruction processing circuit, wherein the second load instruction comprises:
• a second load address register number corresponding to a second load physical register number;
• and
• a second load immediate value;
• and
• determining, by the dependency identifier circuit, that no entries of the store instruction queue store the second load physical register number and the second load immediate value;
• and
• responsive to the dependency identifier circuit determining that no entries of the store instruction queue store the second load physical register number and the second load immediate value:
• determining, by a dependency predictor circuit of the processor device, that a prior occurrence of a read-after-write (RAW) hazard occurred as a result of out-of-order execution of a second store instruction and a second load instruction;
• and
• responsive to determining that the prior occurrence of the RAW hazard occurred, establishing, by the dependency predictor circuit, a dependency between the second store instruction and the second load instruction.

A non-transitory computer-readable medium, having stored thereon computer-executable instructions that, when executed by a processor device, cause a dependency identifier circuit of the processor device to:

• detect a first store instruction in a front end of an instruction processing circuit of the processor device, wherein the first store instruction comprises:
• a single store address register number mapped to a store physical register number;
• and
• a store immediate value;
• write the store physical register number, the store immediate value, and an age indicator in an entry of a plurality of entries of a store instruction queue;
• subsequently detect a load instruction in the front end of the instruction processing circuit, wherein the load instruction comprises:
• a single load address register number mapped to a load physical register number;
• and
• a load immediate value;
• determine whether a first one or more entries of the store instruction queue store the load physical register number and the load immediate value;
• responsive to determining that the first one or more entries of the store instruction queue store the load physical register number and the load immediate value:
• select an entry of the first one or more entries, based on corresponding one or more age indicators of the first one or more entries;
• and
• establish a dependency between the load instruction and a store instruction corresponding to the selected entry;
• and
• responsive to determining that no entries of the store instruction queue store the load physical register number and the load immediate value, cause a dependency predictor circuit of the processor device to:
• determine whether a prior occurrence of a read-after-write (RAW) hazard occurred as a result of out-of-order execution of the first store instruction and the load instruction;
• and
• responsive to determining that the prior occurrence of the RAW hazard occurred, establish a dependency between the first store instruction and the load instruction.