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AssigneeHitachi, Ltd.
InventorsYuki TANAKA, Kotaro SHIMAMURA, Kosuke TODA
Estimating the term…
An information processing device includes speed-up circuits that execute specific arithmetic operation processing, a CPU that holds a plurality of pieces of transfer data to be transferred to one or a plurality of the speed-up circuits and a plurality of data transfer commands for an instruction to transfer the transfer data to one or a plurality of the speed-up circuits, a plurality of data write circuits that are provided for the respective speed-up circuits, each of which writes the transfer data to the speed-up circuit, a write destination determination circuit that outputs a write instruction signal for an instruction to write the transfer data to the speed-up circuit, to one or a plurality of the data write circuits according to the data transfer command output from the CPU, and a data transfer circuit that transfers the transfer data output from the CPU to each of the data write circuits.
An information processing device comprising:
An information processing method in an information processing device including a plurality of speed-up circuits that execute specific arithmetic operation processing, a CPU that holds a plurality of commands including a plurality of pieces of transfer data to be transferred to one or a plurality of the speed-up circuits and a data transfer command for an instruction to transfer the transfer data to one or a plurality of the speed-up circuits, and a plurality of data write circuits that are provided for the respective speed-up circuits, each of which writes the transfer data to the speed-up circuit, the information processing method comprising:
Dependencies are inferred from the claim text.