Register allocation decision
AssigneeArm Limited
InventorsRami Mohammad Al Sheikh, Rodney Wayne Smith, Kiran Ravi Seth, Michael David Achenbach
Life of this patent
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Abstract
An apparatus comprises execution circuitry configured to execute a given instruction to produce a given data value. Value analysis circuitry is configured to perform an analysis of the given data value produced by the execution circuitry to determine at least one property of the given data value, and register allocation circuitry is configured to make a register allocation decision regarding storage of the given data value in a physical register file in dependence on the analysis of the given data value.
Claims17
An apparatus, comprising:
- execution circuitry configured to execute a given instruction to produce a given data value;
- value analysis circuitry configured to perform an analysis of the given data value produced by the execution circuitry to determine at least one property of the given data value;
- and
- register allocation circuitry configured to make a register allocation decision regarding storage of the given data value in a physical register file in dependence on the analysis of the given data value;
- wherein
- the at least one property comprises a width of the given data value, the width indicating a number of bits required to represent the given data value produced by the execution circuitry, and the physical register allocation circuitry is configured to make the register allocation decision in dependence on the width of the given data value;
- the register allocation circuitry comprises a register rename table configured to store entries providing a mapping between a destination architectural register identifier specified by an instruction and a renamed register identifier;
- and
- in response to determining that the width of the given data value is below a given threshold, the register allocation circuitry is configured to store the given data value in an entry of the rename table corresponding to a given destination architectural register specified by the given instruction and skip storing the given data value in the physical register file.
A non-transitory computer-readable medium storing computer-readable code for fabrication of an apparatus, comprising:
- execution circuitry configured to execute a given instruction to produce a given data value;
- value analysis circuitry configured to perform an analysis of the given data value produced by the execution circuitry to determine at least one property of the given data value;
- and
- register allocation circuitry configured to make a register allocation decision regarding storage of the given data value in a physical register file in dependence on the analysis of the given data value;
- wherein
- the at least one property comprises a width of the given data value, the width indicating a number of bits required to represent the given data value produced by the execution circuitry, and the physical register allocation circuitry is configured to make the register allocation decision in dependence on the width of the given data value;
- the register allocation circuitry comprises a register rename table configured to store entries providing a mapping between a destination architectural register identifier specified by an instruction and a renamed register identifier;
- and
- in response to determining that the width of the given data value is below a given threshold, the register allocation circuitry is configured to store the given data value in an entry of the rename table corresponding to a given destination architectural register specified by the given instruction and skip storing the given data value in the physical register file.
A method, comprising:
- executing, with execution circuitry, a given instruction to produce a given data value;
- performing, with value analysis circuitry, an analysis of the given data value to determine at least one property of the given data value;
- and
- making, with register allocation circuitry, a register allocation decision regarding storage of the given data value in a physical register file in dependence on the analysis of the given data value;
- wherein
- the at least one property comprises a width of the given data value, the width indicating a number of bits required to represent the given data value produced by the execution circuitry, and the physical register allocation circuitry is configured to make the register allocation decision in dependence on the width of the given data value;
- the register allocation circuitry comprises a register rename table configured to store entries providing a mapping between a destination architectural register identifier specified by an instruction and a renamed register identifier;
- and
- the method comprises, in response to determining that the width of the given data value is below a given threshold, storing the given data value in an entry of the rename table corresponding to a given destination architectural register specified by the given instruction and skipping storing the given data value in the physical register file.
Dependencies are inferred from the claim text.