G06F 9/3858
Result writeback, i.e. updating the architectural state or memory
Official title: {Result writeback, i.e. updating the architectural state or memory}
G06F9/3858 (Result writeback, i.e. updating the architectural state or memory) appears on 1,802 US grants and 1,302 published applications in this corpus.
Search patents in G06F- Granted patents
- 1,802
- Published applications
- 1,302
- Assignees
- 236
- Inventors
- 2,219
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 1 | 0 |
| 1987 | 1 | 0 |
| 1988 | 1 | 0 |
| 1989 | 2 | 0 |
| 1990 | 1 | 0 |
| 1991 | 4 | 0 |
| 1992 | 3 | 0 |
| 1993 | 6 | 0 |
| 1994 | 13 | 0 |
| 1995 | 20 | 0 |
| 1996 | 46 | 0 |
| 1997 | 63 | 0 |
| 1998 | 103 | 0 |
| 1999 | 101 | 0 |
| 2000 | 82 | 0 |
| 2001 | 78 | 11 |
| 2002 | 63 | 42 |
| 2003 | 54 | 45 |
| 2004 | 47 | 73 |
| 2005 | 47 | 49 |
| 2006 | 50 | 51 |
| 2007 | 51 | 65 |
| 2008 | 53 | 73 |
| 2009 | 50 | 50 |
| 2010 | 56 | 38 |
| 2011 | 71 | 47 |
| 2012 | 31 | 38 |
| 2013 | 39 | 60 |
| 2014 | 32 | 57 |
| 2015 | 34 | 59 |
| 2016 | 95 | 94 |
| 2017 | 69 | 110 |
| 2018 | 84 | 74 |
| 2019 | 70 | 46 |
| 2020 | 61 | 42 |
| 2021 | 63 | 43 |
| 2022 | 42 | 34 |
| 2023 | 45 | 36 |
| 2024 | 21 | 22 |
| 2025 | 26 | 20 |
| 2026 | 21 | 23 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Systems, methods, and apparatuses for heterogeneous computing29 Sep 2026US 12,748,618 B2Intel Corporation
- Register allocation decision8 Sep 2026US 12,730,647 B2Arm Limited
- Performing memory dependency identification without previously encountered read-after-write (RAW) hazards in processor devices18 Aug 2026US 12,710,962 B2QUALCOMM Incorporated
- Self-provisioning and flexible hardware accelerator architecture4 Aug 2026US 12,699,569 B2Infineon Technologies AG
- Instruction conversion device, instruction conversion method, instruction conversion system, and processor for converting extended instructions based on an emulation flag7 Jul 2026US 12,675,292 B2Shanghai Zhaoxin Semiconductor Co., Ltd.
- Information processing device, information processing system, and information processing method1 Oct 2026US 2026/0300191 A1Hitachi, Ltd.
- Instruction conversion method and processor17 Sep 2026US 2026/0277611 A1Shanghai Zhaoxin Semiconductor Co., Ltd.
- System on chip, instruction system, compilation system, and related product13 Aug 2026US 2026/0236265 A1Shanghai Cambricon Information Technology Co., Ltd.
- Processor with delayed instruction pipeline flush23 Jul 2026US 2026/0211678 A1Rivos Inc.
- Shared memory access method and device, computer equipment, storage medium, and program product9 Jul 2026US 2026/0195126 A1
Most cited
By later US patents
- Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags403US 5,226,126 ANexgen Microsystems · 1993
- High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations320US 5,651,125 AAdvanced Micro Devices, Inc. · 1997
- System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache299US 5,136,697 AAdvanced Micro Devices, Inc. · 1992
- RISC architecture computer configured for emulation of the instruction set of a target computer288US 5,574,927 AInternational Meta Systems, Inc. · 1996
- Performance throttling to reduce IC power consumption278US 5,719,800 AIntel Corporation · 1998