Performance throttling to reduce IC power consumption

A microprocessor with controlled power consumption, comprising:

• an activity threshold memory configured to store a dynamically alterable threshold;
• a cache memory operable to store information also stored in an external memory and operable in a normal mode and in a reduced-power mode;
• an activity monitor, coupled to said cache memory, operable to produce an activity level indicative of utilization of said cache memory;
• and
• a mode controller, coupled to said activity threshold memory and to said activity monitor, operable to place said cache memory in said reduced-power mode when said activity level is greater than said activity threshold.

A microprocessor with controlled power consumption, comprising:

• a data-computation unit, operable to perform computations on data stored in an external memory;
• a data cache, coupled to said data-computation unit and to said external memory, operable to store said data;
• an activity monitor, coupled to said data cache, operable to indicate the recent utilization of said data cache;
• an instruction-execution unit, operable to execute instructions from said external memory;
• an instruction cache, coupled to said instruction-execution unit and to said external memory, operable to store said instructions and operable in a normal mode and in a reduced-power mode;
• and
• a mode controller, coupled to said instruction cache and to said activity monitor, operable to place said instruction cache in said reduced-power mode when said recent utilization is greater than a threshold.

A microprocessor with controlled power consumption, comprising:

• an instruction-execution unit, operable to speculatively execute instructions;
• an activity monitor, coupled to said instruction-execution unit, operable to indicate the recent utilization of said instruction-execution unit;
• and
• a mode controller, coupled to said instruction-execution unit and to said activity monitor, operable to throttle said speculative instruction execution, and not to throttle non-speculative instruction execution, when said recent utilization is greater than a threshold.

An IC having controlled power consumption, comprising:

• a functional unit operable in a normal mode and in a reduced-power mode;
• an activity monitor, coupled to said functional unit, operable to indicate utilization of said functional unit;
• and
• a mode controller, coupled to said functional unit and to said activity monitor, operable to place said functional unit in said reduced-power mode when said utilization is greater than a threshold indicated by a throttling parameter associated with said functional unit, said throttling parameter being dynamically adjustable to alter said threshold.

An integrated circuit with controlled power consumption, comprising:

• a functional means for performing a function operable in a normal mode and in a reduced-power mode;
• a monitor means, coupled to said functional means, for calculating an activity level indicative of utilization of said functional means;
• and
• a control means, coupled to said functional means and to said monitoring means, operable to place said functional means in said reduced-power mode when said activity level is greater than a predetermined threshold, the predetermined threshold being dynamically adjustable.

A method of controlling power consumption within an integrated circuit (IC), comprising:

• monitoring utilization of a functional unit within said IC;
• dynamically adjusting an activity threshold associated with the functional unit;
• comparing said utilization with said activity threshold;
• placing said functional unit in a normal mode when said utilization is less than said activity threshold;
• and
• placing said functional unit in a reduced-power mode when said utilization is greater than said activity threshold.

An integrated circuit (IC) having controlled power consumption, comprising:

• a first functional unit within said IC;
• a second functional unit within said IC, said second functional unit being operable in a normal mode and in a reduced-power mode and having an activity level related to an activity level of the first functional unit;
• an activity monitor within said IC, coupled to said first functional unit, operable to produce an activity level indicative of the activity level of said first functional unit;
• and
• a controller within said IC, coupled to said second functional unit and to said activity monitor, operable to place said second functional unit in said reduced-power mode when said activity level of said first functional unit is greater than a threshold.

An integrated circuit (IC) having controlled power consumption, comprising:

• a plurality of functional units each operable in a normal mode and in a reduced-power mode;
• a plurality of local power controllers, each associated with at least one of said functional units and each having throttling parameters, operable to control the power consumption of said associated functional unit in accordance with the current values of said throttling parameters;
• and
• a power coordinator, coupled to at least two of said local power controllers, operable to read a throttling parameter in a first one of said coupled local power controllers and, based thereon, operable to alter a throttling parameter in a second one of said coupled local power controllers.

An integrated circuit (IC) with power consumption controllable by a processor, comprising:

• a functional unit operable in a normal mode and in a reduced-power mode;
• an activity monitor, coupled to said functional unit, having a throttling parameter, operable to generate an activity level indicative of utilization of said functional unit;
• a memory unit configured to store a throttling parameter, said throttling parameter being dynamically alterable by said processor, and
• a mode controller, coupled to said functional unit and to said activity monitor, operable to control said mode of said functional unit responsive to said activity level and to said throttling parameter.