RISC architecture computer configured for emulation of the instruction set of a target computer

A RISC architecture computer having a native instruction width of N bits configured for emulating target instructions from the instruction set of a target computer, comprising:

• a plurality of emulation registers capable of corresponding to registers in the target computer and having data widths greater than or equal to the data widths of the registers in the target computer;
• a plurality of indirect registers for selection of said emulation registers;
• parsing means to extract a plurality of data fields from a target instruction, at least one said field including an opcode;
• dispatching means using said opcode to direct the RISC architecture computer to select at least one M+N bit expanded RISC instruction from a microcode memory;
• an expanded instruction decoder for using said M bits from each said expanded RISC instruction to redefine the RISC architecture computer in terms of the target computer, wherein said M bits define fields, said fields comprising a width field for designating the data width of said emulation registers and the data width of an arithmetic function, an indirect register field for designating said indirect registers, and a condition code field for designating a condition code emulation mode;
• and
• condition code calculation means for determining the condition code for an arithmetic function according to said condition code field.

A RISC architecture computer having a native instruction width of N bits configured for emulating target instructions from the instruction set of a target computer, comprising:

• a plurality of emulation registers capable of corresponding to registers in the target computer and having data widths greater than or equal to the data widths of the registers in the target computer;
• a plurality of indirect registers for selection of said emulation registers;
• parsing means to extract a plurality of data fields from a target instruction, at least one said field including an opcode;
• dispatching means using said opcode to direct the RISC architecture computer to select at least one M+N bit expanded RISC instruction from a microcode memory;
• an expanded instruction decoder for using said M bits from each said expanded RISC instruction to redefine the RISC architecture computer in terms of the target computer;
• and
• condition code calculation means for determining the condition code for an arithmetic function in accordance with the target computer.