Processor with delayed instruction pipeline flush

A processor comprising:

• a plurality of control registers (CRs);
• an instruction processing pipeline operationally coupled with the plurality of CRs, the instruction processing pipeline being configured to execute a plurality of machine-readable instructions based on respective information stored in the plurality of CRs, the plurality of machine-readable instructions including a plurality of CR instructions and a plurality of non-CR instructions;
• and
• a pipeline flush control unit operationally coupled with the instruction processing pipeline, the pipeline flush control unit being configured to:
• record, in response to the instruction processing pipeline completing execution of a first instruction, an indication of the first instruction, the first instruction being a first CR instruction of the plurality of CR instructions;
• identify a second instruction in the instruction processing pipeline prior to completing execution of the second instruction;
• determine, based on a set of predetermined criteria, whether the second instruction conflicts with the first CR instruction;
• and
• if the second instruction is determined to conflict with the first CR instruction, initiate flushing of the instruction processing pipeline.

A method of processing machine-readable instructions, the method comprising:

• completing, in an instruction processing pipeline of a processor, execution of a first instruction of the machine-readable instructions;
• determining, by the processor in response to completing the execution of the first instruction, that flushing of the instruction processing pipeline can be delayed;
• recording an indication of the first instruction;
• examining the instruction processing pipeline to identify a second instruction of the machine-readable instructions in the instruction processing pipeline prior to completing execution of the second instruction;
• determining, based on a set of predetermined criteria, whether the second instruction conflicts with the first instruction;
• and
• if the second instruction is determined to conflict with the first instruction, initiating flushing of the instruction processing pipeline.

A processor comprising:

• a plurality of control registers;
• an instruction processing pipeline operationally coupled with the plurality of control registers, the instruction processing pipeline being configured to execute a plurality of machine-readable instructions based on respective information stored in the plurality of control registers;
• and
• a pipeline flush control unit operationally coupled with the instruction processing pipeline, the pipeline flush control unit and the instruction processing pipeline being configured to:
• record, in response to the instruction processing pipeline completing execution of a first instruction, an indication of the first instruction, the first instruction being configured to write to a first control register of the plurality of control registers;
• identify a second instruction in the instruction processing pipeline prior to completing execution of the second instruction;
• determine, based on a set of predetermined criteria, that the second instruction does not conflict with the first instruction;
• complete execution of the second instruction;
• identify a third instruction in the instruction processing pipeline;
• determine, based on the set of predetermined criteria, that the third instruction conflicts with the first instruction;
• and
• in response to the determination that the third instruction conflicts with the first instruction, initiate flushing of the instruction processing pipeline prior to completing execution of the third instruction.