Shared memory access method and device, computer equipment, storage medium, and program product

A shared memory (SM) access device, comprising:

• a receiving circuit configured to receive an SM reduction instruction, wherein instruction information in the SM reduction instruction comprises address information, an operation code, and source data;
• a judging circuit configured to perform an equal-reduction judgment on valid lanes according to address information in the SM reduction instruction and split the valid lanes according to a result of the equal-reduction judgment, wherein the address information is configured to indicate addresses of the valid lanes;
• a reading circuit configured to read data from the SM according to split results of the valid lanes, wherein the split result is associated with the number of times the data need to be read from the SM;
• and
• a reduction circuit configured to perform a reduction operation according to the data read from the SM, the source data and the operation code in the SM reduction instruction and write a result of the reduction operation into the SM.